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Andreas Olofsson
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@ -2,9 +2,7 @@
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ELINK INTRODUCTION
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=====================================
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The "elink" is a low-latency/high-speed interface for communicating between
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FPGAs and ASICs (such as Epiphany). The interface can achieve a peak
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throughputof 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs.
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The "elink" is a low-latency/high-speed interface for communicating between FPGAs and ASICs (such as Epiphany). The interface can achieve a peak througput of 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs.
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###STRUCTURE
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@ -51,11 +49,7 @@ elink
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```
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###I/O PROTOCOL
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The default elink communication protocol uses source synchronous clocks, a
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packet frame signal, 8-bit wide dual data rate data bus, and separate read
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and write packet wait signals to implement a gluless point to point link. The
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elink has a modular structure allowing the default communication protocol to
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be easily changed by modifying the "etx_protocol" and "erx_protcol" blocks.
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The default elink communication protocol uses source synchronous clocks, a packet frame signal, 8-bit wide dual data rate data bus, and separate read and write packet wait signals to implement a gluless point to point link. The elink has a modular structure allowing the default communication protocol to be easily changed by modifying the "etx_protocol" and "erx_protcol" blocks.
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```
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___ ___ ___ ___ ___ ___ ___ ___
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@ -91,32 +85,15 @@ B15 | data[23:16] in 64 bit write burst mode only
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++B09: is the last byte of 32 bit write or read transaction
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+++B14: is the first data byte of bursting transaction
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The rising edge FRAME signal (sampled on the positive edge of LCLK) indicates
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the start of a new transmission. The byte captured on the first positve
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clock edge of the new packet is B00. If the FRAME control signal
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stays high after B13, then the the elink automatically enters
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“bursting mode”, meaning that the last byte of the previous transaction
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(B13) will be followed by B06 of a new transaction.
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The rising edge FRAME signal (sampled on the positive edge of LCLK) indicates the start of a new transmission. The byte captured on the first positve clock edge of the new packet is B00. If the FRAME control signal stays high after B13, then the the elink automatically enters “bursting mode”, meaning that the last byte of the previous transaction (B13) will be followed by B06 of a new transaction.
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Read and write wait signals are used to stall transmission when a receiver is
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unable to accept more transactions. The receiver will raise its WAIT output
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signal during an active transmission indicating that it can receive only one
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more transaction. The wait signal seen by the transmitter is of unspecified
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phase delay (while still of the LCLK clock period) and therefore has to be
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sampled with the two-cycle synchronizer. If the transaction is in the middle
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of the transmission when the synchronized WAIT control goes high, the
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transmission process is to be completed without interruption.
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Read and write wait signals are used to stall transmission when a receiver is unable to accept more transactions. The receiver will raise its WAIT output signal during an active transmission indicating that it can receive only one more transaction. The wait signal seen by the transmitter is of unspecified phase delay (while still of the LCLK clock period) and therefore has to be sampled with the two-cycle synchronizer. If the transaction is in the middle of the transmission when the synchronized WAIT control goes high, the transmission process is to be completed without interruption.
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###SYSTEM SIDE PROTOCOL
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Communication between the elink and the system side (i.e. the AXI side) is done
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using 104 bit parallel packet interfaces. Read, write, and read response
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transactions have independent channels into the elink. Data from a receiver
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read request is expected to return on the read response transmit chanel.
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Communication between the elink and the system side (i.e. the AXI side) is done using 104 bit parallel packet interfaces. Read, write, and read response transactions have independent channels into the elink. Data from a receiver read request is expected to return on the read response transmit chanel.
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The "access" signals indicate a valid transaction. The wait signals indicate
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that the receiving block is not ready to receive the packet. An elink packet
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has the following bit ordering.
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The "access" signals indicate a valid transaction. The wait signals indicate that the receiving block is not ready to receive the packet. An elink packet has the following bit ordering.
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PACKET FIELD | BITS | DESCRIPTION
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--------------|---------|----------
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@ -136,11 +113,10 @@ The elink has the following clock domains:
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*txo_lclk_div: Used for the etx_core logic
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*rxi_lclk: Used by the erx_io for clocking in dual data rate data at pins
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*txo_lclk: Used by the etx_io for transmitting dual rate data at pins
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*txo_lclk90: The txo_lclk phase shifted by 90 degrees. Used by RX to sample
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the dual data rate data.
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*txo_lclk90: The txo_lclk phase shifted by 90 degrees. Used by RX to sample the dual data rate data.
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###I/O INTERFACE
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###INTERFACE SIGNALS
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SIGNAL |DIR| DESCRIPTION
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------------------|---|--------------
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@ -154,27 +130,17 @@ rxi_lclk{p/n} | I | RX clock aligned in the center of the data eye
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rxi_data{p/n}[7:0]| I | RX dual data rate (DDR) that transmits packet
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rxo_rd_wait{p/n} | O | RX push back (output) for read transactions
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rxo_wr_wait{p/n} | O | RX push back (output) for write transactions
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###AXI INTERFACE
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The AXI master and slave interfaces are use standard signals, but not all
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AXI interconnect features are supported.
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###SYSTEM SIDE INTERFACE
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SIGNAL |DIR| DESCRIPTION
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------------------|---|--------------
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reset | I | Reset input
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pll_clk | I | Clock input for CCLK/LCLK PLL
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sys_clk | I | System clock for FIFOs
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embox_not_empty | O | Mailbox not empty (connect to interrupt line)
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embox_full | O | Mailbox is full indicator
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m_* |IO | AXI master interface
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s_* |IO | AXI slave interface
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###REGISTER MAP
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The full 32 bit physical address of an elink register is the address seen below
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added to the 12 bit elink ID that maps to address bits 31:20. As an example,
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if the elink ID is 0x810, then writing to the E_RESET register would be done to
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address 0x810F0200. Redback is done through the txrd channel wit the source address sub field set to 810Dxxxx;
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The full 32 bit physical address of an elink register is the address seen below added to the 12 bit elink ID that maps to address bits 31:20. As an example, if the elink ID is 0x810, then writing to the E_RESET register would be done to address 0x810F0200. Redback is done through the txrd channel wit the source address sub field set to 810Dxxxx;
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REGISTER | AC | ADDRESS | DESCRIPTION
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---------------|----|---------|------------------
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@ -356,8 +322,7 @@ FIELD | DESCRIPTION
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[15:0] | TBD
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###ERX_GPIO (0xF0308)
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RX status register
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Data sampled on rxi_data and rxi_frame pins in gpio mode
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RX status register. Data sampled on rxi_data and rxi_frame pins in gpio mode
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -372,16 +337,14 @@ FIELD | DESCRIPTION
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[31:0] | Memory offset
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###E_MAILBOXLO (0xF0310)
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Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. This
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register should be read before the E_MAILBOXHI.
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Lower 32 bit word of current entry of RX 64-bit wide mailbox FIFO. This register should be read before the E_MAILBOXHI.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Lower data of RX FIFO
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###E_MAILBOXHI (0xF0314)
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Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this
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register causes the RX FIFO read pointer to increment by one.
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Upper 32 bit word of current entry of RX 64-bit wide mailbox FIFO. Reading this register causes the RX FIFO read pointer to increment by one.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -408,16 +371,14 @@ FIELD | DESCRIPTION
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| 1: Left shifts stride by 16 bits
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###DMACOUNT (0xF0504/0xF0524)
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The number of DMA left to complete The DMA transfer is complete when the
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DMACOUNT register reaches zero.
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The number of DMA left to complete The DMA transfer is complete when the DMACOUNT register reaches zero.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | The number of transfers remaining
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###DMASTRIDE (0xF0508/0xF0528)
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Two signed 16-bit values specifying the stride, in bytes, used to update the
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DMASRCADDR and DMADSTADDR after each completed transfer.
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Two signed 16-bit values specifying the stride, in bytes, used to update the DMASRCADDR and DMADSTADDR after each completed transfer.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -464,8 +425,7 @@ FIELD | DESCRIPTION
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###ETX_MMU (0xE0000)
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A table of N entries for translating incoming 12 bit address
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to a new value. Entries are aligned on 8 byte boundaroies
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A table of N entries for translating incoming 12 bit address to a new value. Entries are aligned on 8 byte boundaries
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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@ -473,8 +433,7 @@ FIELD | DESCRIPTION
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[43:12] | Output address bits 63:32 (TBD)
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###ERX_MMU (0xE8000)
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A table of N entries for translating incoming 12 bit address to a new value.
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Entries are aligned on 8 byte boundaries.
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A table of N entries for translating incoming 12 bit address to a new value. Entries are aligned on 8 byte boundaries.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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