Refactoring mio

- changing datapath name to mio_dp (new methodology)
- top level should be complete block (with control + clock) for ease uf use
- clock renaming

mio/hdl/mio_dp.v

@@ -1,4 +1,4 @@
-module mio (/*AUTOARG*/
+module mio_dp (/*AUTOARG*/
    // Outputs
    tx_full, tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty,
    tx_access, tx_packet, rx_wait, wait_out, access_out, packet_out,
@@ -99,6 +99,7 @@ module mio (/*AUTOARG*/
 	.rx_packet			(rx_packet[N-1:0]),
 	.wait_in			(wait_in));
       
-endmodule // mio
+endmodule // mio_dp
+
 
 

mio/hdl/mtx.v

@@ -43,12 +43,15 @@ module mtx (/*AUTOARG*/
    /*AUTOINPUT*/
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			empty;			// From fifo of oh_fifo_cdc.v
    wire			fifo_access;		// From fifo of oh_fifo_cdc.v
    wire [PW-1:0]	fifo_packet;		// From fifo of oh_fifo_cdc.v
    wire			fifo_wait;		// From par2ser of oh_par2ser.v
+   wire			full;			// From fifo of oh_fifo_cdc.v
    wire			io_access;		// From par2ser of oh_par2ser.v
    wire [2*N-1:0]	io_packet;		// From par2ser of oh_par2ser.v
    wire			io_wait;		// From mtx_io of mtx_io.v
+   wire			prog_full;		// From fifo of oh_fifo_cdc.v
    // End of automatics
 
    //########################################
@@ -77,6 +80,9 @@ module mtx (/*AUTOARG*/
 	  .wait_out			(wait_out),		 // Templated
 	  .access_out			(fifo_access),		 // Templated
 	  .packet_out			(fifo_packet[PW-1:0]),	 // Templated
+	  .prog_full			(prog_full),
+	  .full				(full),
+	  .empty			(empty),
 	  // Inputs
 	  .nreset			(nreset),		 // Templated
 	  .clk_in			(clk),			 // Templated
@@ -126,10 +132,7 @@ module mtx (/*AUTOARG*/
    //########################################
    //# FAST IO (DDR)
    //########################################
-   /*mtx_io  AUTO_TEMPLATE (
-    .clk	(io_clk),
-    );
-   */
+ 
    mtx_io #(.N(N))
    mtx_io (/*AUTOINST*/
 	   // Outputs
@@ -138,7 +141,7 @@ module mtx (/*AUTOARG*/
 	   .io_wait			(io_wait),
 	   // Inputs
 	   .nreset			(nreset),
-	   .clk				(io_clk),		 // Templated
+	   .io_clk			(io_clk),
 	   .ddr_mode			(ddr_mode),
 	   .tx_wait			(tx_wait),
 	   .io_access			(io_access),

mio/hdl/mtx_io.v

@@ -5,7 +5,7 @@ module mtx_io (/*AUTOARG*/
    // Outputs
    tx_packet, tx_access, io_wait,
    // Inputs
-   nreset, clk, ddr_mode, tx_wait, io_access, io_packet
+   nreset, io_clk, ddr_mode, tx_wait, io_access, io_packet
    );
 
    //#####################################################################
@@ -17,7 +17,7 @@ module mtx_io (/*AUTOARG*/
    
    //reset, clk, cfg
    input           nreset;        // async active low reset
-   input           clk;           // clock from divider
+   input           io_clk;           // clock from divider
    input 	   ddr_mode;      // send data as ddr
       
    //IO interface
@@ -42,14 +42,14 @@ module mtx_io (/*AUTOARG*/
    
    //synchronize reset to io_clk
    oh_rsync oh_rsync(.nrst_out	(io_nreset),
-		     .clk	(clk),
+		     .clk	(io_clk),
 		     .nrst_in	(nreset));
    
    //########################################
    //# ACCESS (SDR)
    //########################################
 
-   always @ (posedge clk or negedge io_nreset)
+   always @ (posedge io_clk or negedge io_nreset)
      if(!io_nreset)
        tx_access   <= 1'b0;
      else
@@ -60,13 +60,13 @@ module mtx_io (/*AUTOARG*/
    //########################################
 
    // sampling data for sdr
-   always @ (posedge clk)
+   always @ (posedge io_clk)
      if(io_access)
        tx_packet_sdr[N-1:0] <= byte0_sel ? io_packet[N-1:0] :
 	                                io_packet[2*N-1:N];   
 
    //select 2nd byte (stall on this signal)
-   always @ (posedge clk)
+   always @ (posedge io_clk)
      if(~io_access)
        byte0_sel <= 1'b0;
      else if (~ddr_mode)
@@ -81,7 +81,7 @@ module mtx_io (/*AUTOARG*/
    
    oh_oddr#(.DW(N))
    data_oddr (.out	(tx_packet_ddr[N-1:0]),
-              .clk	(clk),
+              .clk	(io_clk),
 	      .ce	(io_access),
 	      .din1	(io_packet[N-1:0]),
 	      .din2	(io_packet[2*N-1:N])