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Making latch interface generic

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- Should look like a standard cell gate
This commit is contained in:
Andreas Olofsson 2016-04-11 11:58:54 -04:00
parent 5304fd2df2
commit fef2bdbe08
2 changed files with 32 additions and 98 deletions
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68
src/common/hdl/oh_lat0.v
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@ -1,55 +1,21 @@
// # rising edge FF (output in_sl) follwowed by falling edge FF
// # has the following schematic representation:
// #
// # posedge FF -> negedge FF
// # || ||
// # \/ \/
// # lat0-lat1 -> lat1-lat0
// # ||
// # \/
// # lat0-lat1 -> lat0
// # || ||
// # \/ \/
// # posedge FF -> lat0
module oh_lat0 (/*AUTOARG*/
// Outputs
out_sh,
// Inputs
in_sl, clk
);
parameter DW=99;
input [DW-1:0] in_sl;
input clk;
output [DW-1:0] out_sh;
reg [DW-1:0] out_real_sh;
/* verilator lint_off COMBDLY */
// # Real lat0
always @ (clk or in_sl)
if (~clk)
out_real_sh[DW-1:0] <= in_sl[DW-1:0];
/* verilator lint_on COMBDLY */
`ifdef DV_FAKELAT
// # negedge FF
reg [DW-1:0] out_dv_sh;
always @ (negedge clk)
out_dv_sh[DW-1:0] <= in_sl[DW-1:0];
assign out_sh[DW-1:0] = out_dv_sh[DW-1:0];
// #########################################
`else // !`ifdef DV_FAKELAT
// #########################################
assign out_sh[DW-1:0] = out_real_sh[DW-1:0];
// #########################################
`endif // !`ifdef CFG_FAKELAT
//#############################################################################
//# Function: Latch data when clk=0 #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat0 #(parameter DW = 1) // data width
( input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
reg [DW-1:0] out;
always @ (clk or in)
if (!clk)
out[DW-1:0] <= in[DW-1:0];
endmodule // oh_lat0

62
src/common/hdl/oh_lat1.v
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@ -1,53 +1,21 @@
// # falling edge FF (output in_sh) follwowed by rising edge FF
// # has the following schematic representation:
// #
// # negedge FF -> posedge FF
// # || ||
// # \/ \/
// # lat1-lat0 -> lat0-lat1
// # ||
// # \/
// # lat1-lat0 -> lat1
// # || ||
// # \/ \/
// # negedge FF -> lat1
module oh_lat1 (/*AUTOARG*/
// Outputs
out_sl,
// Inputs
in_sh, clk
);
//#############################################################################
//# Function: Latch data when clk=1 #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
parameter DW=99;
module oh_lat1 #(parameter DW = 1) // data width
( input clk, // clk, latch when clk=1
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=0)
);
input [DW-1:0] in_sh;
input clk;
output [DW-1:0] out_sl;
// # lat_clk is created in the following way:
// # 1. clk_en -> lat0 -> clk_en_sh
// # 2. lat_clk = clk_en_sh & clk
reg [DW-1:0] out_real_sl;
wire [DW-1:0] out_sl;
/* verilator lint_off COMBDLY */
// # Real lat1
always @ (clk or in_sh)
reg [DW-1:0] out;
always @ (clk or in)
if (clk)
out_real_sl[DW-1:0] <= in_sh[DW-1:0];
/* verilator lint_on COMBDLY */
out[DW-1:0] <= in[DW-1:0];
`ifdef DV_FAKELAT
// # posedge FF
reg [DW-1:0] out_dv_sl;
always @ (posedge clk)
out_dv_sl[DW-1:0] <= in_sh[DW-1:0];
assign out_sl[DW-1:0] = out_dv_sl[DW-1:0];
endmodule // oh_lat1
`else
assign out_sl[DW-1:0] = out_real_sl[DW-1:0];
`endif // !`ifdef CFG_FAKELAT
endmodule // lat1