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Author SHA1 Message Date
aolofsson
b8a962e61b Fixing random compile issue with -y include in surelog 2022-10-17 21:06:59 -04:00
aolofsson
f21be19c28 Simplifying bin2gray converter 2022-10-17 21:05:55 -04:00
aolofsson
5744252f91 Updating broken fifo (wip) 2022-10-05 08:36:41 -04:00
aolofsson
69a0dd2d3d Fixing broken empty signal 
- Snuck in during the wip changes
 2022-10-04 19:25:59 -04:00
aolofsson
b741fcb3a9 Adding sc place holder 2022-09-29 22:21:04 -04:00
aolofsson
2ae7a67710 Improving help for lfsr module 2022-06-29 08:56:11 -04:00
aolofsson
40756aa177 Merge branch 'master' of github.com:aolofsson/oh 2022-06-28 23:23:01 -04:00
aolofsson
9410821818 Finally converging on a decent lfsr module 
- Lesson 1: Keep it simple!!!
- Lesson 2: Make each program do one thing well. (unix)
- Lesson 3: Make module dynamic (parameters and ifdefs are horrible!)
- Lesson 4: Synthesis can remove bits set to 0 in design...
- Lesson 5: Dynamic binding/programmabiility is better!
 2022-06-28 23:19:56 -04:00
aolofsson
26caf997d3 Finishing minimal icarus "standardized" testbench 
- Driving all values from the command line
- Standardizing around "OH_" to avoid name conflicts
- Driving seed as a parameter value
 2022-06-28 23:18:00 -04:00
aolofsson
8ccce92551 Name change... 
- Calling a random number generator is overstepping..
 2022-06-28 21:19:16 -04:00
Andreas.Olofsson
6b0cb3b24d Hard coding values in oh_verify 
-Match up with stimulus. You can always construct your own using oh_random
 2022-06-27 16:37:17 -04:00
aolofsson
7ba6be5a2f Adding siganture checker 
- Dead simple, just recreate the same lfsr pattern at destination
 2022-06-27 09:28:29 -04:00
aolofsson
5076694f60 New random number generator (wip) 2022-06-27 09:28:06 -04:00
aolofsson
4b95578d9c Making stimulus module more general 
- Drive random stimulus, from memory, or bypass
 2022-06-27 00:27:22 -04:00
aolofsson
e8bbc6a675 Adding Top level simulation file for icarus 
- Very thin file with simulation control specific to simulators
- A similar file needed for Verilator
- The idea is that the testbench can be instantiated in an FPGA/Verilator
 2022-06-27 00:26:09 -04:00
aolofsson
ada97a78be Changing testbench hiearchy 
- A testbench now continaines a dut, standard stimulus module, and in place logic for checking the result.
- The result checking in verilog is the hardest part and generally not done well.
- For verilator/systemc, we rbing out the checking into software through the interface.
- For simple testing like rng based testing or self checking cpu tests, we add the check in verilog at the testbench level on a per dut basis.
 2022-06-27 00:24:07 -04:00
aolofsson
a94911808a Changing testbench to be a stub 2022-06-27 00:23:48 -04:00
aolofsson
3ad1b03fe7 Removing dut feedback loop from simulation control 
- ...to complicated...
- incloding a simple linear test flow for "80%" of foofoo testing
-
 2022-06-27 00:22:02 -04:00
aolofsson
aeb133be6f Making stimulus memory a portable RAM 
-Cleaing up some comments and spacing...
 2022-06-24 22:41:52 -04:00
aolofsson
ed8a53cdd2 Moving simctrl to testbench 
- Cleaning up interfaces
- Adding more universal parameters to testbench top
 2022-06-24 22:40:28 -04:00
aolofsson
4b3a48a01a Adding testbench to be used in fpga/sim 2022-06-24 22:19:33 -04:00
aolofsson
822fa009b8 Refactoring simulation control file 
- Better names (clk1/clk2 was confusing)
- Removing supplies (rare special case), handle with ctrl
- Remove sting passing parameters for testname, primitive, not useuful
 2022-06-24 22:17:42 -04:00
aolofsson
17cbf190dc Adding stub file for tb_dut wrapper 2022-06-24 22:17:21 -04:00
aolofsson
354148d176 Fixing cdc linter error 2022-06-23 17:50:14 -04:00
Andreas.Olofsson
19f278ddb3 Changing name dv to testbench 
-Clarity...
 2022-06-22 11:12:51 -04:00
Andreas.Olofsson
e631bfe3f1 Fixing naming error 
-The directory should contain rtl only.
-HDL is too broad a term
 2022-06-22 11:04:54 -04:00
aolofsson
62e519b52a Directory strcuture change 
-hdl-->rtl (more common...)
 2022-06-21 14:59:53 -04:00
aolofsson
289024fd89 Flattening directory tree (again) 
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
 2022-06-21 14:48:48 -04:00
aolofsson
60fdcbd3e6 Renaming enoc to emesh for consistency 2022-06-18 08:51:24 -04:00
aolofsson
f938b7acac Shorter, better names for rams 2022-06-17 23:16:07 -04:00
aolofsson
19074173ff Making stimulus a general purpose test vector engine 
-Should work in an FPGA as well...
-Anything that is synthesizable goes into the hdl/rtl directory...
 2022-06-17 23:04:34 -04:00
aolofsson
996d980059 Adding testbench for stimulus 
-New name, new methodology
 2022-06-17 23:03:32 -04:00
aolofsson
f0d0750dae Adding test template for emesh packet format 2022-06-17 23:01:40 -04:00
aolofsson
1d7dd09b19 Rallying around TARGET for any platform specific RTL 2022-06-17 15:10:19 -04:00
aolofsson
f0372e5afe Adding random pulse generator 2022-06-17 15:10:03 -04:00
aolofsson
d380374049 Adding basic limits to random number generator 2022-06-17 15:09:32 -04:00
aolofsson
70bbde9ccb Adding basic random HW random number generator 
-work in progress...
 2022-06-17 14:40:24 -04:00
aolofsson
a31e16fb25 Increasing timeout value on simctrl to reasonable default 2022-06-17 14:39:23 -04:00
aolofsson
f6610a0f80 Updating emesh monitor 
- Removing hard coded name in file (dumb)
- Adding support for multiple packet sizes
 2022-06-17 12:56:46 -04:00
aolofsson
46310f842e Changing block name to avoid conflict with "soft" constraints 2022-06-12 22:48:14 -04:00
aolofsson
5258c5c357 Adding place holder isolation buffers 2022-05-29 09:21:10 -04:00
aolofsson
e89f815b38 Going back to placing all folders in src 
- Only way to scale, final decision!!
 2022-05-29 08:45:00 -04:00
aolofsson
d8b44971b5 Fixing old WIP typo bug 2022-05-29 08:43:44 -04:00
aolofsson
818ad00d3c Moving mathlib into stdlib 
-Less libraries is better in this case
 2022-05-27 22:01:24 -04:00
Andreas Olofsson
23b26c4a93
Merge pull request #111 from nmoroze/master 
Some tweaks to padring library
 2021-11-26 21:15:20 -05:00
Noah Moroze
a7bae72f34 Pass through tech_cfg_width to iobuf 2021-10-08 18:53:47 +00:00
Noah Moroze
172c1f8732 Make tech_cfg an inout so it can expose tieoffs 2021-10-07 18:32:20 +00:00
aolofsson
24e70f55bd Confusing to have more than one clock for a sync fifo... 2021-09-25 22:35:42 -04:00
aolofsson
5d4ad5b17b Merge branch 'master' of github.com:aolofsson/oh 2021-09-23 09:58:21 -04:00
aolofsson
eb16df1e3c Fixing syntax errors found by surelog 2021-09-23 09:58:08 -04:00