aolofsson
289024fd89
Flattening directory tree (again)
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- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00
Andreas Olofsson
7094173ae9
Reorg! Why?
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- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
2016-03-22 08:13:40 -04:00
Andreas Olofsson
a4f4881ccf
Adapting ememory to new single port memory interface
2016-02-26 16:59:41 -05:00
Andreas Olofsson
a68bba1572
Cleaning up register interface
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- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
2016-01-11 17:35:53 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
3d49e9ef98
Making AW primary parameter
2015-12-17 12:53:48 -05:00
Andreas Olofsson
51fb4ad4a4
Changing memory parameter to DEPTH
2015-12-04 03:38:51 -05:00
Andreas Olofsson
de012ec9c8
Changes to oh common modules
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- Converting some modules to be more ASIC friendly
2015-12-04 03:12:07 -05:00
Andreas Olofsson
19fa611bb9
Massive reorganization to impove reuse
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- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
0fc4b6188a
Test cleanup
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- added lint script using verilator
- adding verilator filter commands for fifo behavioral
- Longer pushbacks in ememory
2015-11-28 20:15:06 -05:00
Andreas Olofsson
d6499aa918
Use parameter to generate random wait statement
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- Needed for multi instantiation
2015-11-24 01:03:04 -05:00
Andreas Olofsson
86f656022d
Adding memcpy mode to transaction generator
2015-11-18 23:26:05 -05:00
Andreas Olofsson
e94acceaa0
Cleaning up random dv env
2015-11-17 17:10:57 -05:00
Andreas Olofsson
ebc55fa0ab
Adding random transaction generator
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!!found critical bug in design!!
2015-11-16 22:02:44 -05:00
Andreas Olofsson
2f9e2910ac
Fixing 64 bit read bug
2015-11-16 22:01:45 -05:00
Andreas Olofsson
c725f5cab6
Fixing memory model for emesh
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- Moving random wait generator into module
- Fixing wait circuit
2015-11-13 16:23:30 -05:00
Andreas Olofsson
847eae23ab
Adding proper read alignment for ememory model
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-Byte/shorts now work
2015-11-12 10:49:40 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
547bf9751f
Adding a utility for generating emesh transactions
2015-11-11 18:13:52 -05:00
Andreas Olofsson
d788e0da2d
Fixing alignment issue on write
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-The epiphany chip memory does alignment on write
2015-11-11 13:59:24 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
3e78d06051
Moving models out of hdl
2015-11-04 19:20:03 -05:00
Andreas Olofsson
6d9d9702d8
Simulation file cleanup
2015-11-03 19:53:43 -05:00
Andreas Olofsson
22714f3d9d
Adding new emesh format files
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* Adding an improved monitor file
* Adding mesh interface (avoids crud logic at top level)
* A emesh packet memory module
2015-11-02 16:14:08 -05:00
Andreas Olofsson
fc31ad57fd
Reorg
2015-06-25 19:52:28 -04:00
