aolofsson
b8a962e61b
Fixing random compile issue with -y include in surelog
2022-10-17 21:06:59 -04:00
aolofsson
f21be19c28
Simplifying bin2gray converter
2022-10-17 21:05:55 -04:00
aolofsson
5744252f91
Updating broken fifo (wip)
2022-10-05 08:36:41 -04:00
aolofsson
69a0dd2d3d
Fixing broken empty signal
...
- Snuck in during the wip changes
2022-10-04 19:25:59 -04:00
aolofsson
b741fcb3a9
Adding sc place holder
2022-09-29 22:21:04 -04:00
aolofsson
2ae7a67710
Improving help for lfsr module
2022-06-29 08:56:11 -04:00
aolofsson
40756aa177
Merge branch 'master' of github.com:aolofsson/oh
2022-06-28 23:23:01 -04:00
aolofsson
9410821818
Finally converging on a decent lfsr module
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- Lesson 1: Keep it simple!!!
- Lesson 2: Make each program do one thing well. (unix)
- Lesson 3: Make module dynamic (parameters and ifdefs are horrible!)
- Lesson 4: Synthesis can remove bits set to 0 in design...
- Lesson 5: Dynamic binding/programmabiility is better!
2022-06-28 23:19:56 -04:00
aolofsson
26caf997d3
Finishing minimal icarus "standardized" testbench
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- Driving all values from the command line
- Standardizing around "OH_" to avoid name conflicts
- Driving seed as a parameter value
2022-06-28 23:18:00 -04:00
aolofsson
8ccce92551
Name change...
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- Calling a random number generator is overstepping..
2022-06-28 21:19:16 -04:00
Andreas.Olofsson
6b0cb3b24d
Hard coding values in oh_verify
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-Match up with stimulus. You can always construct your own using oh_random
2022-06-27 16:37:17 -04:00
aolofsson
7ba6be5a2f
Adding siganture checker
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- Dead simple, just recreate the same lfsr pattern at destination
2022-06-27 09:28:29 -04:00
aolofsson
5076694f60
New random number generator (wip)
2022-06-27 09:28:06 -04:00
aolofsson
4b95578d9c
Making stimulus module more general
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- Drive random stimulus, from memory, or bypass
2022-06-27 00:27:22 -04:00
aolofsson
e8bbc6a675
Adding Top level simulation file for icarus
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- Very thin file with simulation control specific to simulators
- A similar file needed for Verilator
- The idea is that the testbench can be instantiated in an FPGA/Verilator
2022-06-27 00:26:09 -04:00
aolofsson
ada97a78be
Changing testbench hiearchy
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- A testbench now continaines a dut, standard stimulus module, and in place logic for checking the result.
- The result checking in verilog is the hardest part and generally not done well.
- For verilator/systemc, we rbing out the checking into software through the interface.
- For simple testing like rng based testing or self checking cpu tests, we add the check in verilog at the testbench level on a per dut basis.
2022-06-27 00:24:07 -04:00
aolofsson
a94911808a
Changing testbench to be a stub
2022-06-27 00:23:48 -04:00
aolofsson
3ad1b03fe7
Removing dut feedback loop from simulation control
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- ...to complicated...
- incloding a simple linear test flow for "80%" of foofoo testing
-
2022-06-27 00:22:02 -04:00
aolofsson
aeb133be6f
Making stimulus memory a portable RAM
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-Cleaing up some comments and spacing...
2022-06-24 22:41:52 -04:00
aolofsson
ed8a53cdd2
Moving simctrl to testbench
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- Cleaning up interfaces
- Adding more universal parameters to testbench top
2022-06-24 22:40:28 -04:00
aolofsson
4b3a48a01a
Adding testbench to be used in fpga/sim
2022-06-24 22:19:33 -04:00
aolofsson
822fa009b8
Refactoring simulation control file
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- Better names (clk1/clk2 was confusing)
- Removing supplies (rare special case), handle with ctrl
- Remove sting passing parameters for testname, primitive, not useuful
2022-06-24 22:17:42 -04:00
aolofsson
17cbf190dc
Adding stub file for tb_dut wrapper
2022-06-24 22:17:21 -04:00
aolofsson
354148d176
Fixing cdc linter error
2022-06-23 17:50:14 -04:00
Andreas.Olofsson
19f278ddb3
Changing name dv to testbench
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-Clarity...
2022-06-22 11:12:51 -04:00
Andreas.Olofsson
e631bfe3f1
Fixing naming error
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-The directory should contain rtl only.
-HDL is too broad a term
2022-06-22 11:04:54 -04:00
aolofsson
289024fd89
Flattening directory tree (again)
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- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38
Going back to placing all folders in src
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- Only way to scale, final decision!!
2022-05-29 08:45:00 -04:00
aolofsson
d8b44971b5
Fixing old WIP typo bug
2022-05-29 08:43:44 -04:00
aolofsson
818ad00d3c
Moving mathlib into stdlib
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-Less libraries is better in this case
2022-05-27 22:01:24 -04:00
aolofsson
24e70f55bd
Confusing to have more than one clock for a sync fifo...
2021-09-25 22:35:42 -04:00
aolofsson
eb16df1e3c
Fixing syntax errors found by surelog
2021-09-23 09:58:08 -04:00
aolofsson
88dd3be734
Creating mathlib for arithmetic
2021-08-02 18:18:54 -04:00
aolofsson
1fe01b27d2
File cleanup
2021-08-02 17:37:36 -04:00
aolofsson
02ee349faa
Adding stdlib (in place of common)
2021-07-29 11:22:25 -04:00
aolofsson
de63dfd907
Major reorg!
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-stdcells moved to asiclib, doesn't make sense to be vectorized
-common is a stupid name, renamed as stdlib
2021-07-29 11:20:44 -04:00
