aolofsson
289024fd89
Flattening directory tree (again)
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- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00
aolofsson
e89f815b38
Going back to placing all folders in src
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- Only way to scale, final decision!!
2022-05-29 08:45:00 -04:00
Andreas.Olofsson
d6f5de24d7
Changing hierarchy to promote blocks
2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9
Reorg! Why?
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- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
2016-03-22 08:13:40 -04:00
Andreas Olofsson
e549a63a04
Reorg/cleanup
2016-03-08 19:37:42 -05:00
Andreas Olofsson
3f3728b0bf
Removing timescale from file
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-Nasty! Came out of nowhere, I guess compile order changed...
2016-02-26 19:02:43 -05:00
Andreas Olofsson
e2e99bd29d
Adding read count to fifo interface
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-Also removing valid signal, useless..
2016-01-20 10:48:04 -05:00
Andreas Olofsson
0fc4b6188a
Test cleanup
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- added lint script using verilator
- adding verilator filter commands for fifo behavioral
- Longer pushbacks in ememory
2015-11-28 20:15:06 -05:00
Andreas Olofsson
75cef84075
Timescale stuff
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- Need to look into this again, gotchas here
-
2015-11-13 16:25:38 -05:00
Andreas Olofsson
24afa3c9a0
Deleting old files
2015-11-12 11:00:23 -05:00
Andreas Olofsson
a44053fbe1
Adding Xilinx behavioral models for fifo
2015-11-12 09:57:55 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
81b71df54e
Reorg
2015-11-04 19:15:05 -05:00
Andreas Olofsson
a39966d9f1
Adding IP for fifo
2015-10-07 12:04:50 -04:00
Andreas Olofsson
c627827a6b
Fifo cleanup
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-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
0c66100d6d
Adding half full signal to fifo
2015-07-02 15:00:18 -04:00
Andreas Olofsson
51a642a7b7
Adding 32 deep interface fifo for AXI
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-needed to support burst properly
2015-07-02 14:59:57 -04:00
Patrik Lindström
4a749bf2d8
timing fixes
2015-07-01 00:14:46 +02:00
Andreas Olofsson
7b8a9cf474
Adding IP file for async fifo
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-This is the place for all generic IP blocks
2015-05-23 22:24:44 -04:00
