Noah Moroze
eeb0b784c4
Add ring port for tech-specific power-ring signals
2021-08-18 19:31:04 +00:00
Noah Moroze
4942b2509a
Fix typo
2021-08-17 19:34:44 +00:00
Andreas Olofsson
e0abb876da
Merge pull request #110 from nmoroze/master
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Add "tech config" pass-through for technology-specific GPIO configuration
2021-08-15 22:49:09 -04:00
Noah Moroze
b4f1aa3a60
Add generic cell under oh_pads_corner
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To be consistent with how other I/O cells are defined.
2021-08-13 16:18:37 -04:00
Noah Moroze
3e1d6d8e8d
Add parameters to disable POC/cut cells
2021-08-13 16:18:21 -04:00
Noah Moroze
bc9d7f8e55
Insert missing comma
2021-08-07 17:16:40 -04:00
Noah Moroze
d8a28ac153
padring: add pass-through "tech config" for GPIO
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This is an escape hatch for connecting to technology-specific I/O config pins.
2021-08-05 17:22:47 -04:00
Noah Moroze
adb1bf9eae
Fix whitespace in oh_padring
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- Convert tabs to spaces
- Trim trailing whitespace
2021-08-05 15:48:45 -04:00
aolofsson
88dd3be734
Creating mathlib for arithmetic
2021-08-02 18:18:54 -04:00
aolofsson
4643670a08
Adding ASICLIB description
2021-08-02 18:03:51 -04:00
aolofsson
826bf75d2e
Removing depracated script in asiclib
2021-08-02 18:01:55 -04:00
aolofsson
79b1eb5b6c
Adding README for asiclib
2021-08-02 18:00:13 -04:00
aolofsson
1fe01b27d2
File cleanup
2021-08-02 17:37:36 -04:00
aolofsson
02ee349faa
Adding stdlib (in place of common)
2021-07-29 11:22:25 -04:00
aolofsson
de63dfd907
Major reorg!
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-stdcells moved to asiclib, doesn't make sense to be vectorized
-common is a stupid name, renamed as stdlib
2021-07-29 11:20:44 -04:00
aolofsson
3cb916f4b5
Fixing typo bug in csa32
2021-07-28 18:27:21 -04:00
aolofsson
aeb391a186
Fixing module name issue
2021-07-28 18:25:24 -04:00
aolofsson
df731e4e13
Adding asiclib scripts directory
2021-07-28 08:48:15 -04:00
aolofsson
9e41b55f22
Adding default property to all cells
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-Can be used to select between different cells (like sizes) that have the exact same logical function
2021-07-27 22:55:45 -04:00
aolofsson
541ed2fbc8
Fixing csa cell to be single bit
2021-07-27 22:54:00 -04:00
aolofsson
3dbb3755af
Adding asiclib
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-Represent set of cells that need hard coded cells or hard coded gate level designs.
2021-07-27 22:24:40 -04:00
aolofsson
f91d839e11
WIP: Complete refactoring of common lib to support asic cells
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-Changing DW to N for vector width (uniformity, clarity)
-Adding asic cells with SYN statement
-Adding TYPE parameter
-Moving for loops outside of asic gates
-Rename pwr cells to use simpler names
2021-07-26 22:34:03 -04:00
aolofsson
0a875e193c
Removing useless edge detect module
2021-07-26 17:28:52 -04:00
aolofsson
41e5077f06
Removing depracated iobuf cell (now in padring)
2021-07-26 12:02:58 -04:00
aolofsson
50d9ebe637
Implemeting new asic cell approach for latches
2021-07-26 12:01:50 -04:00
aolofsson
f298ded0d0
Removing depracated generic fifo
2021-07-26 11:50:20 -04:00
aolofsson
421fcf6340
Implementign asic cell redirection for clock gates
2021-07-26 11:49:10 -04:00
aolofsson
916d6c8b3d
Implementing asic_cell redirection for csa's
2021-07-26 11:46:05 -04:00
aolofsson
15c65d2282
Adding clockmux2 and clockmux4
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-Cover 99% of all cases clock selectors
2021-07-26 11:44:17 -04:00
aolofsson
10421758bc
Adding asic cell to buffer
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-Note that asic cells should not be vectorized
-Simplifies implementation (per target)
2021-07-26 11:33:12 -04:00
aolofsson
edaa41dac7
Adding asic_add block to abs circuit
2021-07-26 11:32:43 -04:00
aolofsson
e82fdb65a1
Adding asic_add to counter
2021-07-26 11:32:19 -04:00
aolofsson
9e8263b17d
WIP: Making delay programmable based on selector
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-More generatlized than a statically compiled parameter
-Synthesis engine should optimize away redundant logic
2021-07-26 11:30:29 -04:00
aolofsson
f2f1e10ebe
Removing 8b/10b
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-Not curated
2021-07-26 08:47:08 -04:00
aolofsson
2ad5e665d2
Adding asic instantiation to arithmetic blocks
2021-07-26 08:43:05 -04:00
aolofsson
2e42e174d8
Rewrite of oh_tristate
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-The previous implementation was really an io pad buffer, which belongs in the padring library
-New implementation is a true tristate buffer that can be mapped to an stdcell
2021-07-26 08:41:38 -04:00
aolofsson
2424d929f7
Adding behavioral vs asic distinction to shifter/adder
2021-07-26 08:21:09 -04:00
aolofsson
50c1845f30
Adding synthesizable multipler
2021-07-26 08:19:50 -04:00
aolofsson
2dd46abdd1
Fixing compiler warnings
2021-07-25 15:16:52 -04:00
aolofsson
eb162a3bf3
Changing ifdef to generate statement
2021-07-25 15:04:44 -04:00
aolofsson
141505c638
WIP: Significant reorg
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-Fixing compile errors from previous WIP
-Flattening code structure further for ease of navigation
-Changing to "SYN" for synthesizable code
-Name changes for clarity (PS-->SYNCPIPE)
-
2021-07-25 14:46:55 -04:00
aolofsson
6df5f8bdb4
Merge branch 'master' of github.com:aolofsson/oh
2021-07-24 23:30:05 -04:00
aolofsson
59e8d046da
Compilation cleanup
2021-07-24 23:29:50 -04:00
Andreas Olofsson
b52c45d119
Merge pull request #109 from nmoroze/master
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Fix width of padring 'dout' ports
2021-07-24 22:11:39 -04:00
Noah Moroze
b36d31290a
Fix width of padring 'dout' ports
2021-07-06 17:51:24 -04:00
aolofsson
4556136e7b
Removing depracated file
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-Power merged with domain
2021-06-16 17:00:31 -04:00
aolofsson
7a136c39d8
Adding basic padring generator
2021-06-16 10:49:18 -04:00
aolofsson
bbc0e979d2
Whitespace cleanup to domains file
2021-06-16 09:33:13 -04:00
aolofsson
d6e18791b5
Adding place holder core power pad cell
2021-06-15 11:57:48 -04:00
aolofsson
403976b8c9
Adding corner pad place holder
2021-06-15 11:48:39 -04:00
