- Manually merging work from @olajep in PR #85 (too far out of sync)
- Fixing issue with lsbfirst logic
- Adding logic for manual control of slave select
- Fixing status register for polling reads
- Still a timing/glitch issue on mosi, fix it later...
- Ugly to put latch inside the clock mux, there are situations when there is no clock. Need to have complete control over reset and sampling clock, so better to put latch outside of the clock mux..more legoish..
Commit 3fa5fce "Cleaning up fifos" accidentally changed TARGET from XILINX to GENERIC
This commit fixes this problem and moved TARGET assignment to the top level
Fixes CRITICAL WARNING: [Designutils 20-1280] Could not find module 'fifo_async_104x32'.
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
Vivado does not pre-process defines in the module declaration.
The result is that each module with this type of declaration is AutoDisabled by Vivado
Moving the top level define to a localparam fixes this problem
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
Commit 381ba09 adds CFG_ASIC as a primary variable. This commit
allows this to be set in the system_build.tcl script at build time
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
- adding missing reset on pulse/edge detectors
- disconnecting unused signals in spi clockdivider
- changin output to input on spi_slave_io for read data
- Hiding project name, is a true "global". It defines the flavor of the project and will never be overridden at instantiation...so fine
- Adding CFG_ASIC as a default in parameter statement...because generally you need the ability to override but carrying it all the way through the hierarchy is just annoying...
- The act of putting in a synchronizer should be scalar!
- Putting in vectors should be hard and explicit (thus we make them scalars)
- This is in contrast to most other cells which are vectorized by default
- "which one is not like the others applies to this cell"
- Also cleaning up some chip synthesis warnings/errors
-Need to separate between open FPGA design and closed ASIC design.
-NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA.
-For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology
