- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
- Still not 100% on this...but test passes
- Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
Yes it's simple, but youl should never have to rewrite this code
For larger arbiters, too much risk of making a mistake...
Arbitration mistakes aver nasty to find and nasty to debug!
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
