Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
...
- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6b83cdb0d7
Testbench bug fix
...
- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f
Adding infrastructure for axi_elink
...
- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00
Andreas Olofsson
275ed5252f
Adding test for sweeping idelay and testing reads
...
-It works!!!!
2015-11-03 10:30:20 -05:00
Andreas Olofsson
02b22a36f3
Fixing test to conform to new stimulus format
2015-11-02 20:51:03 -05:00
Andreas Olofsson
96abfe3105
Initial register test (still debugging)
2015-11-02 19:27:41 -05:00
Andreas Olofsson
ec9c3d9e44
Delete old files
2015-11-02 16:08:14 -05:00
Andreas Olofsson
34d379ecb9
Adding new "simpler" test infrastruture
...
- build elink with one command
- place all tests in tests/ directory
- new stimulus format followed
- dut_elink.v created
2015-11-02 16:04:46 -05:00
Andreas Olofsson
ccad681b0e
Fixing testbench for new clocks
...
- Yay! Lots of logic removed
- elink passes again!!!
2015-10-07 19:21:36 -04:00
Andreas Olofsson
902ef1b7dd
Removing hack on rx clock
2015-09-30 13:00:14 -04:00
Andreas Olofsson
8c4c730682
added etype to elink instantiation
2015-09-27 08:40:09 -04:00
Andreas Olofsson
d7508f9938
DV cleanup
...
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
2015-09-14 21:58:52 -04:00
Andreas Olofsson
31f6c94857
Removing random wait for now:
...
-the read-after write is annoying
2015-09-14 20:22:18 -04:00
Andreas Olofsson
23e0f60388
cleanup
2015-09-14 13:28:44 -04:00
Andreas Olofsson
0bfd4d85fc
Adding sim parameter
...
-lenth of reset pulse should be driven from sim environment
2015-09-11 18:25:08 -04:00
Andreas Olofsson
090a6c2b1e
Fixing interfaces due to moving idelay ctrl to clock block
2015-09-11 12:15:22 -04:00
Andreas Olofsson
d6f61784b0
Update dv paths
...
-includes inside files (methodology change)
-adding ip paths
2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97
Adding search path for include file
2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b
Adding back a better fufu test vector
2015-07-02 16:46:33 -04:00
Andreas Olofsson
badac2aa76
Name changes for signal grouping
2015-06-25 16:09:05 -04:00
Andreas Olofsson
2cbf91b07b
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
Andreas Olofsson
c9f64a2fb2
Fixing dv to check axi_elink
...
-Need to split these, getting too cumbersome
2015-05-21 22:56:23 -04:00
Andreas Olofsson
a60de7fb30
Adding readback on axi_elink
...
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
2015-05-19 23:53:05 -04:00
Andreas Olofsson
6d9731f14a
Including environment for axi_elink
...
-Should probably split this into separate environments
-Getting bulky and ugly...
2015-05-19 22:06:15 -04:00
Andreas Olofsson
665876cfb4
Adding bursting to test bench
2015-05-18 15:37:46 -04:00
Andreas Olofsson
007797169c
Clock and reset interface changes
2015-05-14 22:43:44 -04:00
Andreas Olofsson
4cd1e36537
Testbench update to include new clocking scheme
2015-05-13 23:30:30 -04:00
Andreas Olofsson
36696e709e
Updates for new interface
...
-shortening to fit new clock
2015-05-12 07:42:56 -04:00
Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
...
-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
...
-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
...
-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
...
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
...
-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6
E16 model cleanup
...
-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
2015-05-02 21:28:09 -04:00
Andreas Olofsson
08b871941d
Adding e16 elink golden reference to dv environment
2015-05-01 17:32:52 -04:00
Andreas Olofsson
d541a261a6
Adding Epiphany16 elink RTL implementation as reference
...
This is pretty big, wonder if anybody will notice?
Why am I doing this?
Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".
For me and everyone else, it becomes part of the open source design verification environment to test the elink.
Enjoy....
2015-05-01 17:14:50 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
...
Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
4ae2c1ecbf
MILESTONE! Working test with new memory map and 2 link system
2015-04-28 16:55:57 -04:00
Andreas Olofsson
6b2d479692
DV environment cleanup
...
-removed floating signals
-blocking ID transactions from reaching memory (should be done in real design as well)
2015-04-28 16:55:12 -04:00
Andreas Olofsson
a2ceb8ff6e
Cleanup, two-link environment working
...
-Write to config registers from RX path now working
2015-04-28 00:47:26 -04:00
Andreas Olofsson
67a05c9363
Fixing floating wait signal bug
2015-04-28 00:46:03 -04:00
Andreas Olofsson
e1a295998f
Adding 2nd elink to dv env
...
-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
2015-04-27 23:45:43 -04:00
Andreas Olofsson
c9124f415b
Added "timeout" to elink interface
...
-Use as error interrupt?
-Is there another method for checking error?
2015-04-27 15:11:56 -04:00
Andreas Olofsson
d0c4e4f3bd
Fixing arbitration issue
...
-Read/write can collide, adding wait pushback for read
2015-04-27 11:14:26 -04:00
