-The current testbench has a big pause between frames, whereas the chip might push out back to back frames with only a single cycle pause between frames. It seems possible that the old logic would have been a problem, since there two incorrect states that took 2 cycles to settle. This would not have been a problem with bursting or frames with many nops between. Let's see....
-The correct way to verify this is to 1.) Improve TX to make performance as good as on the chip (less stalls) 2.) Create a testbench witht the chip reference code.
-In the meantime, we compile and pray...
-This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this.
-Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
- The response time for async fifo was not fast enough due to synchronization, was causing problems when connecting memory/reg directly to output.
- Was found in testbench, but is generally applicable.
- Also simplifying/refactoring names
-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested to work with test/test_regs.emf
-For new register address, see README.md
cc @olajep @peteasa
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
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