FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
1,458 Commits 7 Branches 1 Tag
Commit Graph

1458 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andreas.Olofsson
046480bfb3 Adding enoc common opcode decode file 2020-10-15 10:12:40 -04:00
Andreas.Olofsson
798634a9c5 Renaming emesh as enoc (better description) 2020-10-15 09:38:12 -04:00
Andreas.Olofsson
f6b9f6cad7 Upating packet2emesh with new format. 
-Moving sa0/sa1 in order to simplify
-With the new clean format there is no need for the split
 2020-10-09 22:10:57 -04:00
Andreas.Olofsson
7c05557e6f MILESTONE: Yet another major revision of emesh protocol 
-Remove formats and rally around 16bit CMD,simplicty over optimization!
-Need to think of being scalable enough for 64bit memory and cache coherent systems!!!! The cost of this forward looking compatibility is only 8 bits, when compared to the 128 bits minimum of address/data pair, this is acceptable
 2020-10-09 21:54:33 -04:00
Andreas.Olofsson
558776a3b3 MILESTON: New packet format created for emesh 2020-10-09 13:18:03 -04:00
Andreas.Olofsson
8268480640 MILESTONE: Implemented new packet command 
-AW16 to AW128
 2020-10-07 10:36:37 -04:00
Andreas.Olofsson
0b91be7a75 New extended packet formats for emesh 2020-10-07 09:28:57 -04:00
Andreas.Olofsson
e123650d06 Major change of "wait" to "ready" 
-This will cause a lot of nasty bugs, but it's the right thing to do to be more consistent with standard buses going forward.
-Change is made from access/wait tp valid/ready
 2020-09-26 12:33:13 -04:00
Andreas.Olofsson
a3f08449e2 Simchecker printout fix 2020-09-26 12:32:38 -04:00
Andreas.Olofsson
58aabca0aa IOBUF name changes 
-Separating pullup and pulldown signals
-Changing direction of in/out names to avoid confusion
-direction is now with reference to the core
 2020-09-23 16:49:34 -04:00
Andreas.Olofsson
c215b48a55 Redesining oh_iddr 
-adding separate clock enables
-adding internal clock enable for neg edg sample
-combining q1/q2 legacy interfae into a single output
 2020-09-23 16:48:10 -04:00
Andreas.Olofsson
fda0f35dd9 Name change to packets 
-Using valid signal instead of access, more standardized
 2020-09-23 16:47:13 -04:00
Andreas.Olofsson
f817bb57ec Removing redundant code in async fifo instance 2020-09-23 16:46:46 -04:00
Andreas.Olofsson
acd469e933 Removing extra pipeline dela in ODDR 
-Both din1 and din2 needs to be stable low by driver
-If the inputs are driven by a reg anyway like in the case of a FIFO output or memory, then we just saved a cycle of redundant latency
 2020-09-22 10:57:00 -04:00
Andreas.Olofsson
6be20de08b Day zer big???!!! 
-Can't believe this was missed!!!!!
-Clearly for a dual data rate circuit, a stable low signal should be selected with low clock, that's the definition!
 2020-09-22 10:31:38 -04:00
Andreas.Olofsson
30419a5239 Adding generic IO buffer 2020-09-21 13:54:06 -04:00
Andreas.Olofsson
98b7494678 Future proof emesh format with another byte of controls 
-At 144 bits, it's less than 5% in signals and virtually no power penalty
-The goal is to be completely axi feature compliant
 2020-09-21 09:20:22 -04:00
Andreas.Olofsson
89f995c20c Fixed nasty testbench problem that snuck in 
-The pass fail indicator is always tricky to get right
-In this case diff/done went high on the same cycle so everything was passing..
-Added check for same cyle completion/fail
-Also, changed the top level anme to "testbench", seems more popular
 2020-08-19 19:34:03 -04:00
Andreas.Olofsson
028dcd886d Bug fix, adding missig reset signal 2020-08-17 23:16:06 -04:00
Andreas.Olofsson
ec26479567 Adding missing ports to dual port memory 
-Seems excessive?
 2020-08-17 23:15:00 -04:00
Andreas.Olofsson
bc76414aa5 Fixing crucial reset bug in dsync 2020-08-17 23:14:21 -04:00
Andreas.Olofsson
6d1735d3b9 Fixing a bunch of synthesis issues 
-Better to fix to avoid issues across different synthesis platform
(even if standard would allow if for verilog2005)
 2020-08-17 16:11:42 -04:00
Andreas.Olofsson
6ae99dbba4 Fixing priority problem withy pass/done 
-When diff gets stuck high, test would timeout
 2020-08-17 16:10:03 -04:00
Andreas.Olofsson
58ee16092e Changing simchecker to hex. 
-Not practical for broad use with binary
 2020-08-17 16:09:32 -04:00
Andreas.Olofsson
76e6cd3c15 Fixing concatenation bug 
-Don't use concatenation for generators!
-Will failt for DW=1
 2020-08-14 10:38:03 -04:00
Andreas.Olofsson
5c0df270c5 Belated fix of register file 
-Simulated correctly, but did not synthesize in DC
 2020-08-08 22:23:45 -04:00
Andreas.Olofsson
0d61520268 Fixed issue with DC verilog parser 
-Apparentely "|=" is not allowed??
 2020-08-08 22:22:52 -04:00
Andreas.Olofsson
d7769070fc Adding diff and sticky flag to ease debugging 
-One flag for end of test pass fail
-Seond flag for gtkwave to see where all the fails happen
 2020-07-27 19:56:57 -04:00
Andreas.Olofsson
7abc91751a Fixing basic register file bug 
-Working in simulation but was not synthesizable by DC
 2020-07-27 19:56:11 -04:00
Andreas.Olofsson
9147a49103 Fixing basic carry bug in the csa4:2 
(carry was wrong)
 2020-07-20 22:51:58 -04:00
Andreas.Olofsson
ae6cdc912e Mapping cs42 to csa32 
-Better synthesis results
 2020-07-20 14:50:09 -04:00
Andreas.Olofsson
9ac530e526 Adding indication that test started for regression clarity 2020-07-19 10:12:07 -04:00
Andreas.Olofsson
84e8449cb5 Moving sampling to negedge for clarity 2020-07-14 13:50:24 -04:00
Andreas.Olofsson
126f859908 Adding clock enable for register 
-Removing the ASIC CFG as well...have to rethink that concept, not really working
 2020-07-14 13:48:42 -04:00
Andreas.Olofsson
d7639390f4 Typo fix 2020-04-23 22:44:47 -04:00
Andreas.Olofsson
58eedb914d Cleanup 2020-04-22 23:17:25 -04:00
Andreas.Olofsson
7c0e1bc01f Adding fail criteria to common simulation control infrastucture 
-Preparing for CI and unit tests for all modules
 2020-04-22 23:16:43 -04:00
Andreas.Olofsson
2c106bed5e Moving checker to positive edge 
-This should be synthesizable into FPGAs!
 2020-04-22 23:15:41 -04:00
Andreas.Olofsson
a7870ac9de Cleaned up counter 
-Not functional
 2020-04-22 23:15:12 -04:00
Andreas.Olofsson
d8d2d0c20e Changing dv_checker to oh_simchecker 
-library consistency
 2020-04-22 22:40:43 -04:00
Andreas.Olofsson
cf47e56436 Changing dv_* to oh_* to be consistent 2020-04-22 21:52:37 -04:00
Andreas.Olofsson
d9897a1bec Multi-type multiplier working 
-only reference model implemented
-Next, implement complete algorithm and output partial products
 2020-04-09 21:42:28 -04:00
Andreas.Olofsson
d6b6e1bd76 Adding basic multiplier stub 2020-04-09 14:58:29 -04:00
Andreas.Olofsson
97bc8d08af Name change one last time... 2020-04-07 10:25:54 -04:00
Andreas.Olofsson
8b39f7e444 Fixing register file 
-Changing DW to RW (RW not always equal to DW..)
-Blocking rd_data on valid
-Fixing elemetary bugs based on indices
-Simplifying index code
-Add configurable pipeline stage?
 2020-04-07 10:23:35 -04:00
Andreas.Olofsson
68829c93d0 Adding dumpvar to interface 2020-04-02 22:14:07 -04:00
Andreas.Olofsson
32b103d290 Adding parametrized register file 2020-04-02 22:13:07 -04:00
Andreas.Olofsson
18bb820f56 Merge branch 'master' of github.com:aolofsson/private-oh 2020-03-28 15:40:11 -04:00
Andreas.Olofsson
c271360709 Changing order of RAM array 2020-03-28 15:38:29 -04:00
Andreas.Olofsson
65aa1b061c Rewritten trace script for spike 
-ovpsim is a dead end, good bye
 2020-03-28 15:37:10 -04:00