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Author SHA1 Message Date
Ola Jeppsson
94b73eb2d0 GPIO: Remove old driver template 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-13 13:17:32 +02:00
Andreas Olofsson
30555c5375 Adding nreset to command reg 
- Not 100% sure on this. Ideally I think you would want the ss signal to be the "reset" of all this logic, but the command register gets too tricky.
- Is there an issue in having a async active low reset pin on the this interface. Considering that this is only a problem for the remote fetch logic (which will definitely have a nreset signal) I think this is ok...
 2016-04-12 09:42:52 -04:00
Andreas Olofsson
24957b73d3 Making interrupt 0 non-maskable. 2016-04-11 20:36:58 -04:00
Andreas Olofsson
e6ed2f2855 Cleanup register addresses of PIC 2016-04-11 20:32:42 -04:00
Andreas Olofsson
6c0ce1ff00 Adding README for PIC 2016-04-11 20:31:30 -04:00
Andreas Olofsson
191f3b4db8 Fixing gpio initial use case example 2016-04-11 19:27:23 -04:00
Andreas Olofsson
7ab30d9f9b Initial thoughts on a gpio driver 2016-04-11 15:46:54 -04:00
Andreas Olofsson
101fb7de66 Copyright transfer 
- All OH! code transferred from Adapteva to non-profit Parallella Foundation
 2016-04-11 12:05:29 -04:00
Andreas Olofsson
1a790eaf24 Preparing for safer clock setting changes 2016-04-11 12:04:30 -04:00
Andreas Olofsson
f25aa0ff45 Cleanup after common lib refactoring 
- clockdiv takes no parameter
 2016-04-11 12:03:44 -04:00
Andreas Olofsson
2688bc5aa4 Refactoring common library 
- Updating interfaces to 2005 style
- Adding license pointers to all files
 2016-04-11 12:01:59 -04:00
Andreas Olofsson
5b8328826e Making rsync interface scalar 
- Who ever uses a vectorized reset....
(if you do, use generate...)
 2016-04-11 11:59:18 -04:00
Andreas Olofsson
fef2bdbe08 Making latch interface generic 
- Should look like a standard cell gate
 2016-04-11 11:58:54 -04:00
Andreas Olofsson
5304fd2df2 Fixing compilation errors 2016-04-11 11:13:08 -04:00
Andreas Olofsson
01a74a3db9 Removing ce from oddr 
- Better to turn off clock if you want to save power
- The CE was actually increasing the power by N x by making every data signal a clock :-)
 2016-04-11 10:30:02 -04:00
Andreas Olofsson
f62d7c0975 Vectorizing csa modules 2016-04-11 09:34:57 -04:00
Andreas Olofsson
d2fbbcf341 Enhancing GPIO block 
- implementing interrupt handling
- edge/level support
- moving to single register for "DIR", avoids confusion
- adding ILATCLR for clearing interrupts
- changing to N parameter away from clumsy 64 bit chunk
- if you want longer GPIO, instantiate more vectors
- up to N==AW supported by this model
- trying out more modern Verilog features
 2016-04-10 23:24:26 -04:00
Andreas Olofsson
233a4150dd Fixing remote fetch spi feature 
- Added missing reset
- Using rising edge of ss (after nreset deasserted) as indicator (and command reg is set to fetch)
- Seems like it should be robust across all clk/sclk frequencies. Can use ss high pause to control timing.
-Assumption, reset is asserted until ss has settled on to "high" at powerup...seems like this is a must not just for fetch.
 2016-04-10 20:56:28 -04:00
Andreas Olofsson
e22a32853b Merge branch 'master' of github.com:parallella/oh 2016-04-07 19:08:44 -04:00
Andreas Olofsson
7fc5d7da1c Cleanin up wait signal 
-There were some corner case problems when driving non safe interfaces like the SPI...can't always have the luxuary of a fifo
 2016-04-07 19:07:44 -04:00
Andreas Olofsson
f610a31d42 Cleanup spi readme 2016-04-07 19:05:01 -04:00
Andreas Olofsson
534f847592 Adding SPI examples 2016-04-07 19:03:11 -04:00
Andreas Olofsson
dd238b5356 SPI now with working emesh packet transfers working 
- (see test_basic.emf for example)
- basically works by pushing consecutive bytes into FIFO (104 bits)
- need to make sure the FIFO does not go empty
 2016-04-07 18:46:26 -04:00
Andreas Olofsson
f5104a62ea Launching data on falling edge on default spi mode 
(as it should be...not sure how I missed this)
 2016-04-07 18:44:41 -04:00
Andreas Olofsson
f1babdb680 Fixing spi master pushback bug 2016-04-07 18:44:24 -04:00
Andreas Olofsson
952657dbd5 Reomving redundant emode feature from spi 2016-04-07 18:44:05 -04:00
Andreas Olofsson
0a1690de94 Fixing epiphany spi fetch 
- adding a separate serializer for the remote fetch (cleaner)
- fixing the load signal to load on all bytes while ss low
- removing reset from command register
- review sync for spi...feels ok to use the rising edge of ss to sync to clock
(note, there must be a free running clk for remote fetch)
- adding wait pushback on remote fetch
 2016-04-07 18:39:39 -04:00
Andreas Olofsson
42649ef2c1 SPI slave fixup 
- removing emode (was redundant)
- fixing user regs issue
- adding status bit to poll for returned data on fetch
 2016-04-07 18:38:29 -04:00
Andreas Olofsson
542fec92e9 Completing test for "epiphany" remote read over spi 2016-04-07 18:37:39 -04:00
Andreas Olofsson
ea3c38e189 Adding shutdown signal for macro 
- Needed for proper power management, should not be lumped with config
 2016-04-06 11:53:03 -04:00
Andreas Olofsson
1b512cdbde Removing asic config dependancy 
- No plans for dual ported memory use for now, if this changes and there needs to be differentiation, then this should probably be a parameter rather than define. (since you might want to choose between regs based and macro based depending on size of memory).
 2016-04-06 11:51:03 -04:00
Andreas Olofsson
83c3caf1c4 Adding back resets 
- Was a little overzealous removing resets in module. Note that these problems popped in recently, were no in the original silicon.
 2016-04-06 11:50:09 -04:00
Andreas Olofsson
8c224d6771 Fixing memory macro instantiation 
- too many variations (polarity etc) on memory interface, stay with generics
(repair + config)
- hookup magic happens under the hood
 2016-04-05 22:43:29 -04:00
Andreas Olofsson
1c1a4dae66 Merge branch 'master' of github.com:parallella/oh 2016-04-05 16:10:50 -04:00
Andreas Olofsson
2bc7c82271 Driving realistic power ramp in startup 2016-04-05 16:10:25 -04:00
Andreas Olofsson
65a888963c Fixing power buffer model 2016-04-05 16:09:20 -04:00
Andreas Olofsson
ae98be160e Implementing basic model checking for shutdown logic 2016-04-05 16:08:33 -04:00
Andreas Olofsson
9e57e4c3fd Update README.md 2016-04-04 14:55:55 -04:00
Andreas Olofsson
ff5e5eff5b Fixing basic bug 
-Vector input not accounted for
 2016-04-04 13:37:50 -04:00
Andreas Olofsson
1c4309160f Changing parameter for emesh_if 
-Only one to keep track of (AW)
 2016-04-04 13:35:49 -04:00
Andreas Olofsson
88a743d5a1 Adding design guideline 
- Circuit level blocks/hacks should be separate from logic with interface
 2016-04-04 13:34:48 -04:00
Andreas Olofsson
a71caf2f42 Removing confusing names on signals 
- The c2io, io2c should never be inside the module!
- Use in/out to clarify direction in interface modules
- The signal direction is indicated at the connectoin level (wrapper)...final decision....
 2016-04-04 09:00:38 -04:00
Andreas Olofsson
822bfcbecc Fixing interface for power gate 2016-04-02 22:39:37 -04:00
Andreas Olofsson
93e7e5dbab Changing parameter default to 1 
- Ease of use, not manditory to override default for N=1
 2016-04-01 22:57:12 -04:00
Andreas Olofsson
53e11ec300 Fixing dut_spi interface 
- adding hw_en
- removing mastermode from interface, not needed
 2016-04-01 10:07:01 -04:00
Andreas Olofsson
43b3c32381 Removing DMA from logic 2016-04-01 10:06:28 -04:00
Andreas Olofsson
2263592940 Reorg 2016-03-31 23:06:43 -04:00
Andreas Olofsson
1dc41b79e6 Adding power supply pins to dma (place holder) 2016-03-31 23:05:05 -04:00
Andreas Olofsson
9db6638d68 Cell renaming 
-Getting too many cells, loose grouping helps me find cells.(not formal)
-Clear and major "blocks" should have their own folder structure
 2016-03-31 19:18:38 -04:00
Andreas Olofsson
223f554fcf Adding power gate switch 2016-03-31 19:18:15 -04:00