-If you are going to instantiate a hard instance, you might as well do it right. For tools that generate these interfaces, who cares
-For debugging, nothing is worse than traversing an endless set of wrappers.
-Bigger interfaces are better than more levels
-Now moving to make the names the change, note that since there are many different designs within one SoC/compilation, you will need to have a large if-else somewhere on the design or an automated compiler for each project.
-I saw you have one file asic_mem that contains all the macros in the design with if-else statements inside
-Is there a situation where you would want to decide top what implementtaion you wnt.
-For example, you might want flip-flops sometimes, and other times perhaps a different aspect ratio?
-How to drive the floor-planning, by running experiments, not hard coding!!!
-A designer might want to choose (tall, wide, square, for hard macros)
-Also need to specify hard/soft on a per macro basis
-making IO memory mapped, should be invisible to user!
-don't push micro optimiation onto programmer!
-don't confuse user with implementation concerns, renaming input to input, output to output for packing!
-Remove formats and rally around 16bit CMD,simplicty over optimization!
-Need to think of being scalable enough for 64bit memory and cache coherent systems!!!! The cost of this forward looking compatibility is only 8 bits, when compared to the 128 bits minimum of address/data pair, this is acceptable
-This will cause a lot of nasty bugs, but it's the right thing to do to be more consistent with standard buses going forward.
-Change is made from access/wait tp valid/ready
-Both din1 and din2 needs to be stable low by driver
-If the inputs are driven by a reg anyway like in the case of a FIFO output or memory, then we just saved a cycle of redundant latency
-Can't believe this was missed!!!!!
-Clearly for a dual data rate circuit, a stable low signal should be selected with low clock, that's the definition!
-The pass fail indicator is always tricky to get right
-In this case diff/done went high on the same cycle so everything was passing..
-Added check for same cyle completion/fail
-Also, changed the top level anme to "testbench", seems more popular
