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Author SHA1 Message Date
Andreas.Olofsson
1bd7c552fb Adding basic tesbench for stimulus function 
-testing the tester
 2020-02-03 13:19:21 -05:00
Andreas.Olofsson
b23a63e2ba Adding firmware example for readmemh 2020-02-03 13:16:37 -05:00
Andreas.Olofsson
b057d47d57 Duh, fixing CFG_ASIC issue! 
-It's a global, use ifdef to avoid compilation issues
-No need for generate
 2020-02-02 23:12:19 -05:00
Andreas.Olofsson
e017f0f290 Stimulus write port written 
-Read port half done, looks straight forward
 2020-02-02 23:11:29 -05:00
Andreas.Olofsson
c23862f4a6 Starting general purpose design of stimulus! 
-memory based, generic
 2020-02-02 21:35:15 -05:00
Andreas.Olofsson
2c9fd39c87 Adding python package setup scripts 
-Work in progress, learning
 2020-02-01 09:43:37 -05:00
Andreas.Olofsson
7bd980fca2 Adding include directorys to lib.cmd 2020-02-01 09:07:47 -05:00
Andreas.Olofsson
4d8d7e4855 Cleanup of risc-v 2020-01-28 18:34:35 -05:00
Andreas.Olofsson
df50421c5c Cleaing up OH repo 2020-01-28 18:21:52 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas.Olofsson
036926fda4 Adding openroad repo to README 2020-01-28 18:04:19 -05:00
Andreas Olofsson
998f3021cc Fixed elink platform compile errors 
-Ultrascale changes broke the zynq design
-Adding CFG_PLATFORM variable to control compilation target
v1.0 		2017-11-22 11:32:20 -05:00
Andreas Olofsson
8cc0809580 Merge pull request #102 from wasserfuhr/patch-4 
fixed typos
 2017-05-09 06:38:11 -04:00
RaWa
9c614cdfcb fixed typos 2017-04-25 15:24:23 +02:00
Andreas Olofsson
13ff7c7091 Merge pull request #93 from rnestler/glossary_fix 
docs: Fix GPIO description
 2017-04-24 21:59:31 -04:00
Andreas Olofsson
08c9b61d7d Merge pull request #97 from MattPD/patch-1 
oh_add: Fix typo in the function description
 2017-04-24 21:59:11 -04:00
Andreas Olofsson
b26b9188a3 Merge pull request #94 from wasserfuhr/patch-3 
fixed sort order
 2017-04-24 21:58:49 -04:00
Andreas Olofsson
70a6f14794 Merge pull request #99 from olajep/zcu102 
Zcu102
 2017-04-24 21:57:56 -04:00
Andreas Olofsson
b1946a7c94 Changed license copyright 
The Parallella Foundation was resolved. Too much of a headache to maintain.  Considering a permanent home in an existing foundation like eclipse, or apache, or other? For now assigning to me. History of code copyright: Adapteva-->Parallella Foundation-->Andreas Olofsson

1.) Most of code developed while Andreas Olofsson was employed at Adapteva

2.) 2016: Adapteva board resolution transfered code to Parallella Foundation under leadership of Andreas Olofsson

3.) 2016: Parallella foundation resolved and code copyright transferred to Andreas Olofsson

None of this should matter given the MIT nature of the license....
 2017-04-01 17:50:04 -04:00
Ola Jeppsson
2f91330d0f common/fpga/create_ip.tcl: Fix error when sub-IP is locked 
- Make local temporary copy
- Don't fail if IP is locked (can happen when partname has changed)

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-10 17:00:55 +01:00
Ola Jeppsson
37a38ab486 zcu102: zcu102: Use Petalinux 2016.4 design as base 
Change partname to:
xczu9eg-ffvb1156-1-i-es2

Don't set BOARD_PART.

Remove si570 pl component.

Full path:
petalinux-bsp/xilinx-zcu102-zu9-es2-rev1.0-2016.4/hardware/xilinx-zcu102-zu9-es2-rev1.0-2016.4/

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-09 23:03:51 +01:00
Ola Jeppsson
02955c09a5 zcu102: zcu102: Define oh_verilog_define 
Define oh_verilog_define to CFG_ASIC=0.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:02:10 +01:00
Ola Jeppsson
fbfe55961c fpga/system_build.tcl: Support oh_verilog_define flag 
Workaround for that recent Vivado versions (2016.4) doesn't seem to
support this any longer:
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $foo -objects [get_runs synth_1]

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 23:01:50 +01:00
Ola Jeppsson
ee2e234dae Revert "common/hdl: Fix syntax error when CFG_ASIC is undefined" 
This reverts commit 049a031e47ff2dde7bd12b151649350d56fc2e09.
 2017-02-07 19:11:05 +01:00
Ola Jeppsson
afccd4a38b zcu102: zcu102: Fix Makefile deps and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:47:42 +01:00
Ola Jeppsson
8706590599 zcu102: zcu102: Remove cclk1 port 
Fails implementation since it's unconnected but its IO standard is LVDS.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:45:52 +01:00
Ola Jeppsson
258cda93d2 fpga/system_build.tcl: Create files for SDK 
Create files needed by Xilinx SDK tool for FSBL generation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:44:04 +01:00
Ola Jeppsson
23c2f8b383 fpga/system_build.tcl: Tweak implementation optimization settings 
This is what ADI HDL uses. I trust that they know what they're doing.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:42:20 +01:00
Ola Jeppsson
f7e8ddfe7d fpga/system_build.tcl: Write raw BIN bitstream file 
Write raw BIN bitstream file without metadata, as well as BIT file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:40:01 +01:00
Ola Jeppsson
66d9a97bda fpga/system_build.tcl: Generate timing summaries 
Generate timing summaries for synthesis and implementation.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 18:37:09 +01:00
Ola Jeppsson
b179a70b27 fpga/system_build.tcl: Use $design instead of hardcoded 'system' 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-07 17:38:41 +01:00
Ola Jeppsson
82cab68bc4 zcu102: zcu102_base: Fix Makefile dependencies and clean target 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-06 19:45:01 +01:00
Ola Jeppsson
a73f0ae10c zcu102: Synthesize & create bitstream in FPGA project 
Uncomment line.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
d30411c80d elink: Migrate to Ultrascale+ IO primitives 
Breaks zynq.

TODO:
- Should be configurable so we can support both Zynq and zynqplus
  (Ultrascale+).
- Need to add idelay3 register so we can expose entire tap range for
  ultrascale. 9 bits vs 5 bits for zynq.
- IDELAYCTRL fails DRC (Vivado bug?)
- Use .DELAY_FORMAT("TIME") in IDELAYE3.  Depends on IDELAYCTRL.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
bae0889773 zcu102/fpga: Update README 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
346b08382b ip: fifo_async_104x32: Regenerate IP 
Part changed.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:11 +01:00
Ola Jeppsson
a7aa6ef67f zcu102: Disconnect carrierboard CLKIN_P1 from zcu102_base/cclk 
Fixes synthesis.
zcu102_base/cclk must be tied to *one* package pin.
Need to create a separate clock primitive for CLKIN_P1.
But those pins are for testing, final design should use on-chip
SG-310 oscillator ("REFA").

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 21:17:02 +01:00
Ola Jeppsson
c172977c00 zcu102: hdl: Change IOSTD_ELINK to 1.8v LVDS 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 18:03:56 +01:00
Ola Jeppsson
bf24d4e491 zcu102: Set board part to zcu102 in zcu102_base ip and zcu102 project 
Seems the right FPGA model is:
xczu9eg-ffvb1156-2-i-es2

No way to tell for sure (JTAG doesn't give exact model) without removing
heatsink from board :(
Should be same package pins though.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:59:50 +01:00
Ola Jeppsson
214278ea0b common/fpga/system_init.tcl: Support board_part variable 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:56:43 +01:00
Ola Jeppsson
74eb5be55b zcu102: Add some documentation 
- Carrier board FMC pinout.
- ZCU102 master XDC file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:54:58 +01:00
Ola Jeppsson
d7fee44574 zcu102: Fix constraints 
- Some pin mappings were wrong (don't code when tired).
- Use 1.8v IO standards.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:52:12 +01:00
Ola Jeppsson
06e80284b2 zcu102: Add constraints for SI570 video clock 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-04 17:51:42 +01:00
Ola Jeppsson
049a031e47 common/hdl: Fix syntax error when CFG_ASIC is undefined 
Workaround for:
Recent Vivado (2016.4) synth step seems to have dropped support for
"-verilog_define CFG_ASIC=0"

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 02:26:37 +01:00
Ola Jeppsson
6a50842b46 zcu102: Update block design 
Ports:
Remove HDMI ports.
Remove cclk0 port.
Add cclk0_[pn] (tile 0-7) ports.
Add cclk1_[pn] (tile 8-15) port.
Add clkpd_1p8v port.

Nets:
Connect zcu102_base/cclk to cclk0 and cclk1.
Connect clkpd_1p8v to zcu102_base_0/chip_nreset.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:53:47 +01:00
Ola Jeppsson
094f417f66 zcu102: Add package pins for FMC0 connector 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-03 00:47:18 +01:00
Ola Jeppsson
bac760678c Add zcu102 design 
Work in progress.
Design looks good.
Need to add pin and timing constraints.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-02-01 11:11:37 +01:00
Ola Jeppsson
440005fbc0 common/fpga/create_ip.tcl: Add Ultrascale+ to supported families 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:49:12 +01:00
Ola Jeppsson
12e7b5ad14 ip: fifo_async_104x32: Switch to ultrascale device 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 18:42:47 +01:00
Ola Jeppsson
83a37d2469 ip: fifo_async_104x32: Update to Vivado 2016.4 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2017-01-31 13:42:59 +01:00