- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
- Turns out I had a nasty bug that was masked by using my own RX to loopback the TX. Since the new RX is very benign with a programmable fifo full flag the timing is quite relaxed.
- The legacy elink for e16 has a strict wait policy. When wait is raised high, you must stop pretty much immediately.
- I struggled with testing this bug on the parallella for 2 days.
- Putting together the test environment uncovered the bug in a couple of hours. F**K, I should know better!!
- The axi slave can never drive enough reads to saturate the maxi fifo since it's only sending out one read at a time.
- Changing the system so that a raw elink sits in front of stimulus..
- Turns out there was a bug hidden in the emaxi that can only be found by properly driving a master device with reads. This could not happen in the old environment.
- Note that due to limitations in the esaxi, I had to add the etx_fifo block as an interface (simplest).
- The ESAXI is very limited in that it MUST interface to a fifo with spare entries. (so prog_full). This should be FIXED!
- Minimal test passes, now to try to reproduce the DMA bug..
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
