Andreas Olofsson
c60f9236da
Adding hack model for RDY signal
...
-should probably last for more cycles thatn this?
2015-10-07 19:18:54 -04:00
Andreas Olofsson
0a73ff3fc5
Adding dynamic tap value behavior
2015-10-07 19:18:27 -04:00
Andreas Olofsson
8c9fea0362
Adding async reset behavior
2015-10-07 19:17:59 -04:00
Andreas Olofsson
13bee36d88
Fixing reset behavioral bug
2015-10-07 19:17:35 -04:00
Andreas Olofsson
ad41b25e42
Making reset async
2015-10-07 12:04:15 -04:00
Andreas Olofsson
8311e4a04e
dummy
2015-10-07 11:58:35 -04:00
Andreas Olofsson
790480bedd
Adding dummy cells
2015-10-07 11:57:52 -04:00
Andreas Olofsson
394920a1e7
Addding phase delay tracking
...
- As a dirty a model hack as they come, using positive and negative edge of CLKIN to sample the signal and phase align the clock output.
- Will only work with div 2/4/8 etc
- There may be other issues, have to think about it...
- But the test now passes cleanly and the clocks look good.
2015-09-30 13:40:11 -04:00
Andreas Olofsson
cada5bd9b6
Adding clock tracking on PLL/DLL
...
-Fixed PLL model to make it properly phase aligned with CLKIN
2015-09-14 20:23:25 -04:00
Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
b0c7b75407
Adding OBUF model
2015-06-25 15:42:20 -04:00
Andreas Olofsson
1ec8991e2a
Adding IDELAY elements to xilibs
2015-05-16 22:07:17 -04:00
Andreas Olofsson
cd624d6531
Adding IDDR model
2015-05-15 15:27:45 -04:00
Andreas Olofsson
1f89e682bb
Adding warning regarding clock divider
...
-For now only div by 2/4/8 supported
-Really need to implement general purpose integer clock divider!
2015-05-15 15:26:59 -04:00
Andreas Olofsson
ee363f6119
Fixed ODDR model for SAME_EDGE mode
2015-05-15 09:46:08 -04:00
Andreas Olofsson
836c4a65a8
Adding PLLE2_ADV model
2015-05-14 22:49:42 -04:00
Andreas Olofsson
a2d8c5c453
Adding PLL LOCK functionality
...
-not accurate, but at least it gives some dunmy behavior for PLLLOCK
2015-05-14 22:48:55 -04:00
Andreas Olofsson
58aeb0ee87
Adding warning message to ISERDES/OSERDES
...
-Don't use them!!
2015-05-13 23:33:26 -04:00
Andreas Olofsson
ade946ce90
Updating with new (and correct) modeling
2015-05-13 23:31:52 -04:00
Andreas Olofsson
dc8cb83268
Cleanup
2015-05-07 23:49:50 -04:00
Andreas Olofsson
4f3f9b9de5
Fixing bug in clock frequency parameter
2015-05-07 23:49:07 -04:00
Andreas Olofsson
1d5b967a7f
Adding simulation model for PLL
...
NOTE: Depends on CLKIN machting parameter in model!
For example, if clkin=100MHZ, period parameter must be 10
2015-05-06 12:28:25 -04:00
Andreas Olofsson
3e74d68dcc
Both input and output models were wrong.
...
Should match datasheet now...
2015-05-04 22:35:55 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
...
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
...
Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
62c2c0e654
Adding comments
2015-04-23 17:52:46 -04:00
Andreas Olofsson
35d6c3934f
Comments
2015-04-23 17:52:06 -04:00
Andreas Olofsson
617214cc90
Cleanup
2015-04-22 13:56:29 -04:00
Andreas Olofsson
77d41cfe4e
Adding PLL and MMCME2 primitives
2015-04-22 13:55:59 -04:00
Andreas Olofsson
1508afa2ea
Adding a "max" ps7 system for reference
...
Not convinced that it's good to do this in text...
(but it's always good to know what's underneath the hood)
Vivado IP generates wrappers after all
2015-04-22 13:54:52 -04:00
Andreas Olofsson
f35ed3836d
Only primitiveds in the xilibs (no generated IP)
2015-04-21 21:44:44 -04:00
Andreas Olofsson
ebaac22700
Cleanup
2015-04-21 21:43:16 -04:00
