6 Commits

Author	SHA1	Message	Date
Andreas Olofsson	9bc40a8355	Fixing wait issue ... -Removing the wait signal from the pipeline -Assumption is that the prog_full is used on fifo, allowing two entries to be captured in fifo. -May revisit this at some time...	2015-08-14 17:13:52 -04:00
Andreas Olofsson	ede8656081	Fixing mutual exclusive bug on receiver ... -When a read response is detected, there should be no spurious transactions to the RD/WR request fifos. -Move the "filter" backt to the erx_protocol block -Removed the remap bypass signal (was hacky) -Passes simulations again..	2015-08-14 15:37:37 -04:00
Andreas Olofsson	6ba45155fd	Integrating clock approach change ... -clocks moved outside elink -new packet interface format between protocol and io block	2015-05-13 23:29:18 -04:00
Andreas Olofsson	624d0e6134	Reorg cleanup ... -renamed disty for consistency (there is an arbiter there now) -adding missing ID to etx/erx -New org working!	2015-05-12 07:41:48 -04:00
Andreas Olofsson	81db0b7582	Completing elink hierarchy change ... -splits out clock domains -makes the core portion a clean/reusable module with defined interface	2015-05-10 23:38:08 -04:00
Andreas Olofsson	eaadfc6465	Adding etx/erx core modules ... -Single clock domain -Super-light... -Need to be able to remove internal feature as well -(MMU/DMA should be optional but on by default..)	2015-05-10 23:06:52 -04:00