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395 Commits 7 Branches 1 Tag
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41 Commits

Author SHA1 Message Date
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
c9f64a2fb2 Fixing dv to check axi_elink 
-Need to split these, getting too cumbersome
 2015-05-21 22:56:23 -04:00
Andreas Olofsson
a60de7fb30 Adding readback on axi_elink 
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
 2015-05-19 23:53:05 -04:00
Andreas Olofsson
6d9731f14a Including environment for axi_elink 
-Should probably split this into separate environments
-Getting bulky and ugly...
 2015-05-19 22:06:15 -04:00
Andreas Olofsson
665876cfb4 Adding bursting to test bench 2015-05-18 15:37:46 -04:00
Andreas Olofsson
007797169c Clock and reset interface changes 2015-05-14 22:43:44 -04:00
Andreas Olofsson
4cd1e36537 Testbench update to include new clocking scheme 2015-05-13 23:30:30 -04:00
Andreas Olofsson
36696e709e Updates for new interface 
-shortening to fit new clock
 2015-05-12 07:42:56 -04:00
Andreas Olofsson
d83efbdb8e Cleaning up initial constraints 
-Now generates bit stream
-It won't work, but it's a start...
 2015-05-08 20:56:33 -04:00
Andreas Olofsson
38d7fe1af9 Clock cleanup 
-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
 2015-05-07 23:46:32 -04:00
Andreas Olofsson
4f487d498e Making simulation more "real" 
-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
 2015-05-06 12:21:39 -04:00
Andreas Olofsson
d0439f871f Adding example design for FPGA 2015-05-05 21:37:17 -04:00
Andreas Olofsson
b2846c5312 MILESTONE: Read/write works back and forth 
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
 2015-05-04 17:13:51 -04:00
Andreas Olofsson
72aff72558 MILESTONE: register read/write working! 
-Bullet proof clock domain crossings!
 2015-05-04 10:49:17 -04:00
Andreas Olofsson
56fa70c0dd Connecting wait output from e16_model 2015-05-02 21:29:43 -04:00
Andreas Olofsson
08b871941d Adding e16 elink golden reference to dv environment 2015-05-01 17:32:52 -04:00
Andreas Olofsson
6b2d479692 DV environment cleanup 
-removed floating signals
-blocking ID transactions from reaching memory  (should be done in real design as well)
 2015-04-28 16:55:12 -04:00
Andreas Olofsson
67a05c9363 Fixing floating wait signal bug 2015-04-28 00:46:03 -04:00
Andreas Olofsson
e1a295998f Adding 2nd elink to dv env 
-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
 2015-04-27 23:45:43 -04:00
Andreas Olofsson
c9124f415b Added "timeout" to elink interface 
-Use as error interrupt?
-Is there another method for checking error?
 2015-04-27 15:11:56 -04:00
Andreas Olofsson
d0c4e4f3bd Fixing arbitration issue 
-Read/write can collide, adding wait pushback for read
 2015-04-27 11:14:26 -04:00
Andreas Olofsson
d44ea5d089 Adding monitor for ememory in dv_elink.v 
-Dumps into emem.trace
 2015-04-27 00:06:04 -04:00
Andreas Olofsson
5af7a745b1 Created separate IDs for RX and TX 
-We want to make the two directions as separate as possible so no shared variables. Still need a tag for differentiating between write and read response. In addition we need a group to keep the rr separate from mailbox write.
git diffgit c
 2015-04-23 23:10:27 -04:00
Andreas Olofsson
74fe62e94d Broken testbench connections 2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401 File cleanup 2015-04-23 18:10:07 -04:00
Andreas Olofsson
035b3c9ba5 Milestone: WRITE AND READ FROM HOST WORKS! 2015-04-21 17:16:20 -04:00
Andreas Olofsson
e033e233d0 Integrating emesh memory module 
-This will flush out the final read response path
 2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079 Message box working... 
-More testing needed!
 2015-04-19 21:55:07 -04:00
Andreas Olofsson
7c93c565e9 Adding back awid, arid, lock to AXI interface 2015-04-18 17:35:22 -04:00
Andreas Olofsson
643ceed432 Adding manual test feature to testbench 
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
 2015-04-18 16:14:53 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
69f3df4140 Continued work to create clean design: 
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
 2015-04-15 11:54:43 -04:00
Andreas Olofsson
b58660e9a6 Adding different data modes 
Good enough fufu testing...
..the next step is driving stimulus with transactor through Verilator..
 2015-04-14 23:47:49 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup 
~10 real bugs
-mostly name mismatches and bit range mistakes
 2015-04-14 14:00:23 -04:00
Andreas Olofsson
bf1671b1e9 Added "fufu" DV environment for elink 
-Icarus for now, verilator comes next
-Using our "standard" emesh interface
..here we go...
 2015-04-14 11:45:33 -04:00
Andreas Olofsson
73229ff914 Major cleanup, refactoring, and feature completion 
-adding clock bypass mode for esystx[12]
-removing monitor feature on erx
-remove loopback support from doc
-add clock bypass mode for esysclk
-shortening register names (descriptive enough)
-added debug signal information
-moving registers to elink
-making elink version programmable (to support plug in boards)
-reorganized debug signals and added stickys
-added timeout for axi slave
-removed embox status bit (redudant, don't poll status)
-renamed EMBOX0-->EMBOXLO
-moved datain interface straight to ecfg (cleanup)
-changed etx arbiter priority to increase stability
-created the esaxi_mux block
-fixed some missing ports issues in stubs

Now comes the fun part...verification...
Andreas
 2015-04-11 00:04:18 -04:00
Andreas Olofsson
239ca128c2 Vivado run through 
-missed connections
-mismatched bus widths
-missing IP blocks
-cleanup
-proper DV starts tomorrow
 2015-04-08 23:40:16 -04:00
Andreas Olofsson
a6a5de33c2 Fixing bus issue with datain/dataout signal 
Found in Vivado...
Needed to  connect up the wait signals properly on dataout/datain registers
 2015-04-08 13:20:25 -04:00
Andreas Olofsson
b0b9315bf1 Massive checkin... 
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
 2015-03-24 20:44:03 -04:00
aolofsson
0cd5939a26 Adding fofo environment for elink to check for broken signals. 
Too many stub modules to be practical..next need sim models
 2014-12-14 22:17:23 -05:00