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10 Commits

Author SHA1 Message Date
Andreas Olofsson
643ceed432 Adding manual test feature to testbench
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
2015-04-18 16:14:53 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92 Fixed testbench bug (copy paste, RX not enabled)... 2015-04-17 10:08:17 -04:00
Andreas Olofsson
dca611c5ba Getting all the clk config numbers aligned
Not changing these again!!
2015-04-16 22:48:31 -04:00
Andreas Olofsson
068d63279b Changing ESYSCLK definition (again.....)
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
2015-04-16 22:31:36 -04:00
Andreas Olofsson
b1a9f502ca Xilinx models
-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench
2015-04-15 17:54:19 -04:00
Andreas Olofsson
846bfa3357 Fixing startup issues in transmit path:
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
2015-04-15 16:33:20 -04:00
Andreas Olofsson
b58660e9a6 Adding different data modes
Good enough fufu testing...
..the next step is driving stimulus with transactor through Verilator..
2015-04-14 23:47:49 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
bf1671b1e9 Added "fufu" DV environment for elink
-Icarus for now, verilator comes next
-Using our "standard" emesh interface
..here we go...
2015-04-14 11:45:33 -04:00