Andreas Olofsson
d6f61784b0
Update dv paths
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-includes inside files (methodology change)
-adding ip paths
2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97
Adding search path for include file
2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b
Adding back a better fufu test vector
2015-07-02 16:46:33 -04:00
Andreas Olofsson
badac2aa76
Name changes for signal grouping
2015-06-25 16:09:05 -04:00
Andreas Olofsson
2cbf91b07b
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
Andreas Olofsson
c9f64a2fb2
Fixing dv to check axi_elink
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-Need to split these, getting too cumbersome
2015-05-21 22:56:23 -04:00
Andreas Olofsson
a60de7fb30
Adding readback on axi_elink
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-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
2015-05-19 23:53:05 -04:00
Andreas Olofsson
6d9731f14a
Including environment for axi_elink
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-Should probably split this into separate environments
-Getting bulky and ugly...
2015-05-19 22:06:15 -04:00
Andreas Olofsson
665876cfb4
Adding bursting to test bench
2015-05-18 15:37:46 -04:00
Andreas Olofsson
007797169c
Clock and reset interface changes
2015-05-14 22:43:44 -04:00
Andreas Olofsson
4cd1e36537
Testbench update to include new clocking scheme
2015-05-13 23:30:30 -04:00
Andreas Olofsson
36696e709e
Updates for new interface
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-shortening to fit new clock
2015-05-12 07:42:56 -04:00
Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
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-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6
E16 model cleanup
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-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
2015-05-02 21:28:09 -04:00
Andreas Olofsson
08b871941d
Adding e16 elink golden reference to dv environment
2015-05-01 17:32:52 -04:00
Andreas Olofsson
d541a261a6
Adding Epiphany16 elink RTL implementation as reference
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This is pretty big, wonder if anybody will notice?
Why am I doing this?
Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".
For me and everyone else, it becomes part of the open source design verification environment to test the elink.
Enjoy....
2015-05-01 17:14:50 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
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Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
4ae2c1ecbf
MILESTONE! Working test with new memory map and 2 link system
2015-04-28 16:55:57 -04:00
Andreas Olofsson
6b2d479692
DV environment cleanup
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-removed floating signals
-blocking ID transactions from reaching memory (should be done in real design as well)
2015-04-28 16:55:12 -04:00
Andreas Olofsson
a2ceb8ff6e
Cleanup, two-link environment working
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-Write to config registers from RX path now working
2015-04-28 00:47:26 -04:00
Andreas Olofsson
67a05c9363
Fixing floating wait signal bug
2015-04-28 00:46:03 -04:00
Andreas Olofsson
e1a295998f
Adding 2nd elink to dv env
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-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
2015-04-27 23:45:43 -04:00
Andreas Olofsson
c9124f415b
Added "timeout" to elink interface
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-Use as error interrupt?
-Is there another method for checking error?
2015-04-27 15:11:56 -04:00
Andreas Olofsson
d0c4e4f3bd
Fixing arbitration issue
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-Read/write can collide, adding wait pushback for read
2015-04-27 11:14:26 -04:00
Andreas Olofsson
3567805823
Adding dummy vector to testbench
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-All zeroes is ignored by stimulus
-Easy to remember...
2015-04-27 11:13:53 -04:00
Andreas Olofsson
d44ea5d089
Adding monitor for ememory in dv_elink.v
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-Dumps into emem.trace
2015-04-27 00:06:04 -04:00
Andreas Olofsson
919a5fa5e8
Register map twiddles
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-Fixed test to correspond to new map
2015-04-25 07:09:52 -04:00
Andreas Olofsson
c0d8c967c4
Address remapping integration
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Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
3b637e55f0
MILESTONE: Design once again passes test
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New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
5af7a745b1
Created separate IDs for RX and TX
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-We want to make the two directions as separate as possible so no shared variables. Still need a tag for differentiating between write and read response. In addition we need a group to keep the rr separate from mailbox write.
git diffgit c
2015-04-23 23:10:27 -04:00
Andreas Olofsson
74fe62e94d
Broken testbench connections
2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
ec68dddd99
Packet interface changes
2015-04-23 18:09:16 -04:00
Andreas Olofsson
617214cc90
Cleanup
2015-04-22 13:56:29 -04:00
Andreas Olofsson
ba8f400a37
oops
2015-04-21 21:50:03 -04:00
Andreas Olofsson
c01a9fbd27
Adding basic readme files
2015-04-21 21:49:40 -04:00
Andreas Olofsson
275264c84d
Reorg
2015-04-21 21:33:49 -04:00
Andreas Olofsson
035b3c9ba5
Milestone: WRITE AND READ FROM HOST WORKS!
2015-04-21 17:16:20 -04:00
Andreas Olofsson
b89d6222d8
Adding test for readback from host
2015-04-21 17:15:56 -04:00
Andreas Olofsson
fc3926ceb1
Added wait signal for reads
2015-04-21 17:13:53 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
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-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079
Message box working...
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-More testing needed!
2015-04-19 21:55:07 -04:00
