aolofsson
15c65d2282
Adding clockmux2 and clockmux4
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-Cover 99% of all cases clock selectors
2021-07-26 11:44:17 -04:00
aolofsson
10421758bc
Adding asic cell to buffer
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-Note that asic cells should not be vectorized
-Simplifies implementation (per target)
2021-07-26 11:33:12 -04:00
aolofsson
edaa41dac7
Adding asic_add block to abs circuit
2021-07-26 11:32:43 -04:00
aolofsson
e82fdb65a1
Adding asic_add to counter
2021-07-26 11:32:19 -04:00
aolofsson
9e8263b17d
WIP: Making delay programmable based on selector
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-More generatlized than a statically compiled parameter
-Synthesis engine should optimize away redundant logic
2021-07-26 11:30:29 -04:00
aolofsson
f2f1e10ebe
Removing 8b/10b
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-Not curated
2021-07-26 08:47:08 -04:00
aolofsson
2ad5e665d2
Adding asic instantiation to arithmetic blocks
2021-07-26 08:43:05 -04:00
aolofsson
2e42e174d8
Rewrite of oh_tristate
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-The previous implementation was really an io pad buffer, which belongs in the padring library
-New implementation is a true tristate buffer that can be mapped to an stdcell
2021-07-26 08:41:38 -04:00
aolofsson
2424d929f7
Adding behavioral vs asic distinction to shifter/adder
2021-07-26 08:21:09 -04:00
aolofsson
50c1845f30
Adding synthesizable multipler
2021-07-26 08:19:50 -04:00
aolofsson
2dd46abdd1
Fixing compiler warnings
2021-07-25 15:16:52 -04:00
aolofsson
eb162a3bf3
Changing ifdef to generate statement
2021-07-25 15:04:44 -04:00
aolofsson
141505c638
WIP: Significant reorg
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-Fixing compile errors from previous WIP
-Flattening code structure further for ease of navigation
-Changing to "SYN" for synthesizable code
-Name changes for clarity (PS-->SYNCPIPE)
-
2021-07-25 14:46:55 -04:00
aolofsson
6df5f8bdb4
Merge branch 'master' of github.com:aolofsson/oh
2021-07-24 23:30:05 -04:00
aolofsson
59e8d046da
Compilation cleanup
2021-07-24 23:29:50 -04:00
Andreas Olofsson
b52c45d119
Merge pull request #109 from nmoroze/master
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Fix width of padring 'dout' ports
2021-07-24 22:11:39 -04:00
Noah Moroze
b36d31290a
Fix width of padring 'dout' ports
2021-07-06 17:51:24 -04:00
aolofsson
4556136e7b
Removing depracated file
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-Power merged with domain
2021-06-16 17:00:31 -04:00
aolofsson
7a136c39d8
Adding basic padring generator
2021-06-16 10:49:18 -04:00
aolofsson
bbc0e979d2
Whitespace cleanup to domains file
2021-06-16 09:33:13 -04:00
aolofsson
d6e18791b5
Adding place holder core power pad cell
2021-06-15 11:57:48 -04:00
aolofsson
403976b8c9
Adding corner pad place holder
2021-06-15 11:48:39 -04:00
aolofsson
3601fa409b
Adding place-holder cell for padring
2021-06-15 11:45:10 -04:00
aolofsson
acc72c5762
Removing netlist directory
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-All abstracted information contained in hdl
2021-05-26 14:57:25 -04:00
aolofsson
d0dab83075
Merging rtl and switch models in one verilog file
2021-05-25 19:27:00 -04:00
aolofsson
2eb3e4518b
Prototype for driving cell level parameters
2021-05-25 16:10:50 -04:00
aolofsson
2e8551d468
Adding nor primitive circuit
2021-05-25 13:57:16 -04:00
aolofsson
b2624e803e
Adding switch level modeling of nand gate
2021-05-25 13:48:00 -04:00
aolofsson
3fc3983494
Fixing concatentation errors
2021-05-24 20:56:48 -04:00
aolofsson
9631c50bae
Adding scan cells to standard cell libs
2021-05-24 20:52:04 -04:00
aolofsson
f4184b048a
Adding xor standard cell family
2021-05-24 20:30:20 -04:00
aolofsson
5e151efa51
Adding batch of oa/ao cells
2021-05-24 20:26:05 -04:00
aolofsson
a08ef0d84c
Fixing nset typo
2021-05-24 20:25:55 -04:00
aolofsson
0489dd2d8c
First batch of standard cells
2021-05-24 19:05:20 -04:00
aolofsson
a0625a7d0f
Adding WIP/broken warning
2021-04-26 10:26:24 -04:00
aolofsson
3c6c41ff83
Removing depracated eda directory
2021-04-26 09:39:36 -04:00
Andreas Olofsson
3977791929
Merge pull request #108 from aolofsson/pr_aolofsson
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A long overdue merge of a private branch
2021-04-26 08:58:44 -04:00
aolofsson
65a13b5067
Merge branch 'master' of github.com:aolofsson/private-oh into pr_aolofsson
2021-04-26 08:56:16 -04:00
aolofsson
ff4ddf28d8
Dummy commit
2021-04-26 08:44:21 -04:00
aolofsson
3911ad8c6e
Using autoinst feature for fifo_sync
2021-04-18 22:30:13 -04:00
aolofsson
2ca5343322
Updating latch syntax to fix Foss parsing issues
2021-04-18 22:29:27 -04:00
aolofsson
413d1dec32
Addding full interface to memory
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-If you are going to instantiate a hard instance, you might as well do it right. For tools that generate these interfaces, who cares
-For debugging, nothing is worse than traversing an endless set of wrappers.
-Bigger interfaces are better than more levels
2021-03-02 16:49:49 -05:00
aolofsson
9b63e23bda
Adding always_latch to avoid verilator warnings
2021-03-02 16:49:20 -05:00
Andreas.Olofsson
1925c188c8
Fixing compilation error
2021-03-02 15:36:33 -05:00
Andreas.Olofsson
3e49fa499f
Making almost full programmable in oh_fifo_sync
2020-12-07 16:58:47 -05:00
Andreas.Olofsson
401d1c2e93
Adding a generic single/dual/soft/hard memory macro
2020-12-04 15:58:53 -05:00
Andreas.Olofsson
490ce22244
Flattening memory hierarchy!!!
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-Now completely compatible with FPGA and ASIC flows with a single source
2020-12-04 15:58:07 -05:00
Andreas.Olofsson
7ff50650f7
Changing name back to "oh_mem_dp"
...
-Now moving to make the names the change, note that since there are many different designs within one SoC/compilation, you will need to have a large if-else somewhere on the design or an automated compiler for each project.
-I saw you have one file asic_mem that contains all the macros in the design with if-else statements inside
-Is there a situation where you would want to decide top what implementtaion you wnt.
-For example, you might want flip-flops sometimes, and other times perhaps a different aspect ratio?
-How to drive the floor-planning, by running experiments, not hard coding!!!
-A designer might want to choose (tall, wide, square, for hard macros)
-Also need to specify hard/soft on a per macro basis
2020-12-04 12:39:45 -05:00
Andreas.Olofsson
b62c11cf67
name change from memory_sp to sram_sp
2020-11-02 15:01:50 -05:00
Andreas.Olofsson
022563c414
Name change for enoc packet to avoid signal confusion
2020-11-02 14:54:29 -05:00
