Andreas Olofsson
d0c4e4f3bd
Fixing arbitration issue
...
-Read/write can collide, adding wait pushback for read
2015-04-27 11:14:26 -04:00
Andreas Olofsson
3567805823
Adding dummy vector to testbench
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-All zeroes is ignored by stimulus
-Easy to remember...
2015-04-27 11:13:53 -04:00
Andreas Olofsson
743d3a710d
MMU mi_write bug fix
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MMU should only be written when [15] of address is set
(shares address space with other registers in TX/RX)
2015-04-27 11:12:18 -04:00
Andreas Olofsson
4856e39193
RX address remap bug fix
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-Used the wrong sub vector...
(silly mistake)
2015-04-27 09:29:22 -04:00
Andreas Olofsson
d79447853f
Register name shuffle
2015-04-27 09:28:52 -04:00
Andreas Olofsson
d44ea5d089
Adding monitor for ememory in dv_elink.v
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-Dumps into emem.trace
2015-04-27 00:06:04 -04:00
Andreas Olofsson
3cb8d1d426
Adding test mode registers for transmit path
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Makes it possible to easily test the IO path using the mi_ interface
The mi interface is very simple to drive in logic...
2015-04-27 00:04:30 -04:00
Andreas Olofsson
89286af8a9
Adding documentation of elink protocol
2015-04-26 23:02:13 -04:00
Andreas Olofsson
f7aef66f29
Bug fix: erx pipeline misalignment
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-access signal happens one signal after empty goes low to compensate for fifo data latency
-verify that this is how the Xilinx FIFO works as well.
2015-04-26 08:31:36 -04:00
Andreas Olofsson
21f87edd87
Memory bug fix
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-srcaddr (upper data of read response) was using input instead of output data
-blocking upper data on 32 bit reads and smaller (quieter..)
Need random DV to flush out these silly bugs...
2015-04-26 08:29:50 -04:00
Andreas Olofsson
afd6e86840
Fixing etx pipeline
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-Fixed one bug inserted during edits, causing double transactions
-Added pipeline stall logic to all units
2015-04-25 23:28:52 -04:00
Andreas Olofsson
ca835b9607
tweaking register map again...
2015-04-25 23:28:18 -04:00
Andreas Olofsson
5f595a75d3
Register write bug for new map
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-Need to block access if [15] is one (reserved for emmurx)
2015-04-25 07:10:13 -04:00
Andreas Olofsson
919a5fa5e8
Register map twiddles
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-Fixed test to correspond to new map
2015-04-25 07:09:52 -04:00
Andreas Olofsson
c0d8c967c4
Address remapping integration
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Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
be42ea3b89
Register map change
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-Changed register map
-Splitting into groups, more natural
2015-04-24 17:38:01 -04:00
Andreas Olofsson
79467583c9
Made reset async (there may not be a clock..)
2015-04-24 17:32:17 -04:00
Andreas Olofsson
ea7683693c
Adding RX/TX address remapping
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The MMU is a monster and may be too much
Adding simple remapping modules
Covers todays feature and then some
1.) Static remapping
2.) Addresss compression
2015-04-24 17:29:05 -04:00
Andreas Olofsson
b25ad633f7
Readback cleanup
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RX/TX interfaces should be mininmized and standalone
Adding mux to consolidate to one "dout"
2015-04-24 17:27:35 -04:00
Andreas Olofsson
3b637e55f0
MILESTONE: Design once again passes test
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New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
0ed6afeac9
Added tag and group for read response
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-Still not sure about this..
2015-04-23 23:14:39 -04:00
Andreas Olofsson
370034437f
Added proper 64bit write port to mailbox
2015-04-23 23:14:04 -04:00
Andreas Olofsson
46896c63ef
Bug fix, adding reset signal
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This will blocking when there is no clock at startup.
2015-04-23 23:13:05 -04:00
Andreas Olofsson
24fc91072d
Adding IDs to keep access signals straight
2015-04-23 23:11:58 -04:00
Andreas Olofsson
5af7a745b1
Created separate IDs for RX and TX
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-We want to make the two directions as separate as possible so no shared variables. Still need a tag for differentiating between write and read response. In addition we need a group to keep the rr separate from mailbox write.
git diffgit c
2015-04-23 23:10:27 -04:00
Andreas Olofsson
01fec0f72a
Fixed elink missind ID parameter
2015-04-23 20:07:52 -04:00
Andreas Olofsson
5c8fb41849
Fifo read bug
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-fifo should be read when it's not empty and there is no wait pushback
2015-04-23 20:07:10 -04:00
Andreas Olofsson
c4c1edc10f
Adding reset to critical signals in pipe
2015-04-23 20:06:11 -04:00
Andreas Olofsson
21173fef95
Forgot "posedge reset"
2015-04-23 20:05:51 -04:00
Andreas Olofsson
7ab3b3a8f8
Fixed floating net bug
2015-04-23 20:05:00 -04:00
Andreas Olofsson
74fe62e94d
Broken testbench connections
2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
5ac06cd772
Fixed stupid typos on full/empty
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Surprised it wasn't caught during iverilog compile
2015-04-23 18:56:49 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
ec68dddd99
Packet interface changes
2015-04-23 18:09:16 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3
Changing so basic elink unti is without AXI
2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f
Splitting register file into separate pieces
2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835
Changing to packet interface
2015-04-23 18:07:27 -04:00
Andreas Olofsson
ed0b8c2539
Major RX change:
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-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
Andreas Olofsson
2707541eab
Adding DMA source and changing interface
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-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
2015-04-23 18:03:10 -04:00
Andreas Olofsson
842a6d894a
Fixing enable/reset:
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-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
2015-04-23 18:01:19 -04:00
Andreas Olofsson
7418d45f5e
Cleanup
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-Packet interface change
-Adding RX enable logic with synchronizer (better place than erx_io)
2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4
Major upgrade
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-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094
Packet interface change
2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09
Packet interface change
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-Changed packet interface
-Removed rd/wr from block, was pass through
2015-04-23 17:56:15 -04:00
Andreas Olofsson
31e721cea7
Interface change
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Changed to packet interface
Changed name to "mailbox"
2015-04-23 17:54:59 -04:00
Andreas Olofsson
8266e6dd29
Changing to packet interface
2015-04-23 17:54:23 -04:00
Andreas Olofsson
34813035bc
Changing FIFO interface
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More inline with standard Xilinx fifo
names, names, names..ugh
2015-04-23 17:53:22 -04:00
Andreas Olofsson
62c2c0e654
Adding comments
2015-04-23 17:52:46 -04:00
