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17 Commits 7 Branches 1 Tag
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5 Commits

Author SHA1 Message Date
Fred Huettig
1bc118cfcd Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign 
Conflicts:
	fpga/src/ecfg/hdl/ecfg.v
 2014-11-19 12:29:35 -05:00
Fred Huettig
440d932794 New Vivado-friendly modules, testbench for elink gold-vs-new. 2014-11-19 12:02:18 -05:00
aolofsson
26c5da0cbb Create combined reset (hw+sw) 
Added data select output for axi_slave mux
Signal cleanup (gpio_data)
 2014-11-06 11:52:38 -05:00
aolofsson
536613b230 Changed to 20 bit addressing for clarity in FPGA 2014-11-05 19:49:18 -05:00
aolofsson
4ab49e07c2 Reorganizing structure to be IP centric 
-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
 2014-11-05 14:31:05 -05:00