Andreas Olofsson
1fa3543ba1
Changing back to lower cases, works..
2015-11-06 20:46:41 -05:00
Andreas Olofsson
6e2ee17481
Updated system memory map
2015-11-06 20:44:18 -05:00
Andreas Olofsson
c9dc9c33ee
Almost done connecting
...
- AXI connections not working properly...
2015-11-06 18:26:09 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
8a89b7e185
Adding more structured vivado build files
2015-11-06 14:11:46 -05:00
Andreas Olofsson
84b5af5b3a
Cleanup
2015-11-06 14:10:35 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
...
- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
0fcea92b0d
Scripts per "project"
2015-11-06 06:58:47 -05:00
Andreas Olofsson
90998b8ad0
Adding parallella synthesis scripts
2015-11-06 06:58:14 -05:00
Andreas Olofsson
6cb5f88073
Moving block deisgns into a single Parallella module
...
- Easier to maintain
- Better sandbox
2015-11-06 06:56:56 -05:00
Andreas Olofsson
bc53400888
Adding parallella block design
...
-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
2015-05-22 21:38:39 -04:00
