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mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00

1527 Commits

Author SHA1 Message Date
Peter Saunderson
a8ef3748bd AXI: emaxi: added nreset to instantiation of oh_dsync
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2016-08-17 15:57:25 +01:00
Peter Saunderson
e781f39e5e TARGET changed back to XILINX from GENERIC
Commit 3fa5fce "Cleaning up fifos" accidentally changed TARGET from XILINX to GENERIC
This commit fixes this problem and moved TARGET assignment to the top level
Fixes CRITICAL WARNING: [Designutils 20-1280] Could not find module 'fifo_async_104x32'.

Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2016-08-17 15:30:38 +01:00
Peter Saunderson
553ee31400 Synthesis: parameter = `CFG_ASIC not accepted in module declaration
Vivado does not pre-process defines in the module declaration.
The result is that each module with this type of declaration is AutoDisabled by Vivado

Moving the top level define to a localparam fixes this problem

Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2016-08-17 15:06:01 +01:00
Peter Saunderson
55118cee9d Apply CFG_ASIC at the top level
Commit 381ba09 adds CFG_ASIC as a primary variable.  This commit
allows this to be set in the system_build.tcl script at build time


Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2016-08-17 14:22:04 +01:00
RainerWasserfuhr
b9b42bd93e fixed sort order 2016-08-05 21:49:20 +02:00
Andreas Olofsson
aac3d5b3a2 Synthesis cleanup 2016-07-24 05:11:47 -04:00
Andreas Olofsson
67409dba7a Simplifying names to make it easier to specify generated clocks 2016-07-09 20:32:57 -04:00
Andreas Olofsson
2c272e7afa Synthesis cleanup
- adding missing reset on pulse/edge detectors
- disconnecting unused signals in spi clockdivider
- changin output to input on spi_slave_io for read data
2016-07-09 20:31:00 -04:00
Andreas Olofsson
b8ef013874 Cleanup (missed a port in last fix removing supply ports) 2016-07-09 17:04:24 -04:00
Andreas Olofsson
b1871f1867 Fixing clock divider
- asic needs a fixed cell for generated clock constraints
- fixing glitching on selectors, sampling with latch before mux (stable high)
2016-07-09 17:03:07 -04:00
Andreas Olofsson
6b050220d8 Removing dangling supply nets 2016-07-08 19:56:23 -04:00
Andreas Olofsson
c0dde5652b Merge branch 'master' of github.com:parallella/oh 2016-06-26 10:02:24 -04:00
Andreas Olofsson
f2086c5e69 Asic lib cleanup
-moving back to generic asic cells after all..
-fixing parameter issue in memory module
-named block issue (genblk warning)
2016-06-25 00:04:25 -04:00
Andreas Olofsson
8b95b37c85 The asiclib is not generic
- Should be "gate level"  design
2016-06-24 22:37:06 -04:00
Andreas Olofsson
b4337d9aba Adding flip-flopr asic wrappers 2016-06-24 22:36:27 -04:00
Andreas Olofsson
71f3271074 Adding sampling clock for latch
- Should be independent of the clocks being selected
2016-06-24 22:11:36 -04:00
Andreas Olofsson
56e7037254 Adding clock "or" circuit 2016-06-24 22:11:23 -04:00
Andreas Olofsson
74b26a285f Removing supplies from isolation cells
- Was unnatural
2016-06-24 21:30:34 -04:00
Andreas Olofsson
186b337a45 Cleanup of common files using cells that use asic cells
- ASIC/PROJ changes
2016-06-24 21:26:14 -04:00
Andreas Olofsson
bc515f9308 Adding isolation block for tie high
- Needed for active low reset signal
2016-06-24 21:25:41 -04:00
Andreas Olofsson
a45155a4e6 ASIC config parameter simplication
- Hiding project name, is a true "global". It defines the flavor of the project and will never be overridden at instantiation...so fine
- Adding CFG_ASIC as a default in parameter statement...because generally you need the ability to override but carrying it all the way through the hierarchy is just annoying...
2016-06-24 20:34:49 -04:00
Andreas Olofsson
2623d2239e Adding asiclib cell for lat0 2016-06-24 20:34:32 -04:00
Andreas Olofsson
893db9508a Merge branch 'master' of github.com:parallella/oh
Conflicts:
	docs/tapeout_checklist.md
2016-06-20 21:21:07 -04:00
Andreas Olofsson
b866045861 Making DELAY a cell parameter 2016-06-19 17:36:00 -04:00
Andreas Olofsson
ef2e3248a3 Adding parameter guideline
- You will be chasing this bug, if you ever add a parameter...
2016-06-19 17:35:18 -04:00
Andreas Olofsson
aa1e511a30 Moving xilibs/hdl to xilibs/dv
- HDL should always be synthesizable...
2016-06-19 17:18:44 -04:00
Andreas Olofsson
40da0fe14a Synthesis cleanup 2016-06-19 17:12:24 -04:00
Andreas Olofsson
73c1c496cb Cleaning up SPI chip synthesis errors/warnings
- Better to clean up than to have every designer setting an "ignore warning" in tool.
- Don't fight the tools...
2016-06-19 17:11:33 -04:00
Andreas Olofsson
3151b17b93 Cleaning up chip synthesis errors/warnings 2016-06-19 17:10:51 -04:00
Andreas Olofsson
61980721f6 Changing synchronizers to scalars
- The act of putting in a synchronizer should be scalar!
- Putting in vectors should be hard and explicit (thus we make them scalars)
- This is in contrast to most other cells which are vectorized by default
- "which one is not like the others applies to this cell"
- Also cleaning up some chip synthesis warnings/errors
2016-06-19 17:08:46 -04:00
Andreas Olofsson
381ba09617 Making CFG_ASIC a primary variable
-Need to separate between open FPGA design and closed ASIC design.
-NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA.
-For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology
2016-06-19 17:05:50 -04:00
Andreas Olofsson
1045e46b0e Merge pull request #92 from olajep/mio-driver
Mio driver
2016-06-06 05:12:39 -04:00
Ola Jeppsson
0ccee8f82f mio: hello-mio: More extensive testing
Pushback seems broken somewhere.

Test writing 2 x 1MB

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-06-06 07:40:14 +00:00
Ola Jeppsson
729132b4d3 mio: driver: Add first hello world test
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-06-01 14:54:44 +00:00
Andreas Olofsson
51f5d0f73a Adding link to checklist 2016-05-31 13:33:06 -04:00
Andreas Olofsson
e89acd3002 A few more checks... 2016-05-31 13:31:34 -04:00
Andreas Olofsson
4042168dfa Adding a tapeout checklist 2016-05-31 13:24:40 -04:00
Andreas Olofsson
6911b67189 Adding a tapeout checklist 2016-05-31 13:19:26 -04:00
Andreas Olofsson
74dca550d4 Merge pull request #81 from olajep/gpio-fix
gpio: Fix issue with new emesh packet format
2016-05-19 09:58:04 -04:00
Andreas Olofsson
434b8fd141 Merge pull request #82 from olajep/parallella-oh-gpio-spi-projects-separate-address-space
Parallella oh gpio spi projects separate address space
2016-05-19 09:56:30 -04:00
Ola Jeppsson
15b2e9d6a8 spi: Move out of the way of elink
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-05-19 14:12:15 +02:00
Ola Jeppsson
8a6eb44cd5 gpio: Move out of the way of elink
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-05-19 14:10:47 +02:00
Ola Jeppsson
16a575a84e gpio: Fix issue with new emesh packet format
Vivado complains since AW is 32 bits wide but emesh_readback.read_data
is now 64 bits wide.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2016-05-19 14:06:17 +02:00
Andreas Olofsson
f9613d8d89 Updating dma with new packet format 2016-05-15 15:49:39 -04:00
Andreas Olofsson
d0b5fcdc69 Updating spi to new packet format 2016-05-15 15:48:45 -04:00
Andreas Olofsson
e6071559a0 Updating mio to new packet format 2016-05-15 15:48:31 -04:00
Andreas Olofsson
363a5cf717 Updating gpio for new emesh packet format 2016-05-15 15:47:45 -04:00
Andreas Olofsson
82b6b2fcb1 Updating to new emesh packet mappers 2016-05-15 15:46:49 -04:00
Andreas Olofsson
c78c24899f Updating emesh packet mappers
- modified 64b interface
- adding some other address widths/types
- making AW/PW orthogonal for added flexibility, this means wheneve these blocks are used, you have to specify AW/PW
- making 32/104 the default for backwards compatibility
- changing to v2005 interface
- adding license
2016-05-15 15:45:05 -04:00
Andreas Olofsson
a9708c0ba4 Adding PW to dv interfaces
- Needed for generic relantionship between AW/PW
2016-05-15 15:33:00 -04:00