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Author SHA1 Message Date
Andreas Olofsson
2263592940 Reorg 2016-03-31 23:06:43 -04:00
Andreas Olofsson
1dc41b79e6 Adding power supply pins to dma (place holder) 2016-03-31 23:05:05 -04:00
Andreas Olofsson
9db6638d68 Cell renaming 
-Getting too many cells, loose grouping helps me find cells.(not formal)
-Clear and major "blocks" should have their own folder structure
 2016-03-31 19:18:38 -04:00
Andreas Olofsson
223f554fcf Adding power gate switch 2016-03-31 19:18:15 -04:00
Andreas Olofsson
cfad8dbf17 Adding isolation buffer 2016-03-31 18:30:18 -04:00
Andreas Olofsson
c112c06ddf Adding logical buffer with supply modeling 
- important for multi power supply designs
 2016-03-31 18:21:02 -04:00
Andreas Olofsson
4f5b3ab8a9 Adding hw_en pin to SPI module 
- b/c there are times when you need physical control of the pins (can't do it in software, no packets will arrive)
- use case examples: security, power gating, reliability
 2016-03-30 12:02:05 -04:00
Andreas Olofsson
ab19abd965 Fixing connection errors for AW=64 in SPI 2016-03-28 16:45:10 -04:00
Andreas Olofsson
813dd3c17e Adding wrapper for generic pll 2016-03-28 09:19:14 -04:00
Andreas Olofsson
7b54e6b88f Adding binary decoder 
-Binary to one hot translation
 2016-03-25 22:57:34 -04:00
Andreas Olofsson
d17aa9cad1 Adding 7 segment decode 2016-03-25 22:55:07 -04:00
Andreas Olofsson
01423157bf Merge pull request #58 from prasadp4009/master 
Initial Commit of 8b10b Encoder and Decoder
 2016-03-25 19:19:44 -04:00
Prasad Pandit
1ca2a44140 Initial Commit of 8b10b Encoder and Decoder 
Signed-off-by: Prasad Pandit <prasadp4009@gmail.com>
 2016-03-25 16:04:26 -07:00
Andreas Olofsson
e5665a5bc0 Changing parameter back to NMIO 
- While N is a nice generic parameter, when integrating with a lot of other modules, it was becoming too confusing. The MIO already has three parameters: MPW, PW, and MIO. Important to keep them apart when integrating at the chip level.
 2016-03-25 15:35:48 -04:00
Andreas Olofsson
4b87fdae34 Adding missing parameters statements in mio_if 2016-03-23 20:45:15 -04:00
Andreas Olofsson
ac5a77ec6c Implemented frame polarity in mio 
-Seems like the place to do this, more advanced framing should be done outside of mio
 2016-03-23 08:38:53 -04:00
Andreas Olofsson
9e00240a40 Removed mio autoincrement mode 
-Have this handled in a more capable DMA (no need to duplicate functionality)
-Adding frame polarity signal
 2016-03-23 08:29:41 -04:00
Andreas Olofsson
01f54a859b Adding initial DMA documentation 2016-03-23 00:07:36 -04:00
Andreas Olofsson
4d7bf8cc16 Integrating DMA control logic 2016-03-22 23:49:49 -04:00
Andreas Olofsson
4e9172656d Implemented descriptors, new decode 
- Work in progress, not debugged
 2016-03-22 23:49:01 -04:00
Andreas Olofsson
9bec938914 Implemented DMA state machine 
- Work in progress
 2016-03-22 23:38:16 -04:00
Andreas Olofsson
26515bc1e9 Changing edma register map 
- Removing AUTODMA LAB feature, needed the register space...
- AUTODMA the way it was implemented was lame
 2016-03-22 23:37:23 -04:00
Andreas Olofsson
aae3bfa75a Adding missing clkout1 bypass for divide by one 2016-03-22 23:35:43 -04:00
Andreas Olofsson
9e5367cae9 Merge branch 'master' of github.com:parallella/oh 2016-03-22 16:37:31 -04:00
Andreas Olofsson
e731acc934 Adding DMA 
- First draft
- Work in progress..
 2016-03-22 16:36:23 -04:00
Andreas Olofsson
824c92f942 Merge pull request #57 from olajep/idelay-fix 
elink/sw/idelay: Update for ESDK 2016.3
 2016-03-22 14:10:22 -04:00
Ola Jeppsson
75d33b1c0e elink/sw/idelay: Update for ESDK 2016.3 
- ee_{write,read}_esys removed from e-hal, implement in idelay.
- Access to FPGA regs restricted by driver.
  Need to pass unsafe_access parameter to module.

If builtin, add to bootargs:
epiphany.unsafe_access

If module:
sudo rmmod epiphany && sudo modprobe epiphany unsafe_access

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-03-22 18:03:29 +00:00
Andreas Olofsson
d9ea47a88d Common library cleanup 2016-03-22 09:19:39 -04:00
Andreas Olofsson
6f60b19c8f Adding links to all common modules 2016-03-22 09:17:01 -04:00
Andreas Olofsson
401bc8319a README formatting 2016-03-22 08:32:09 -04:00
Andreas Olofsson
c3b83621e0 Reorg cleanup 2016-03-22 08:27:59 -04:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
a6f1dc8971 Merge branch 'master' of github.com:parallella/oh 2016-03-22 08:01:04 -04:00
Andreas Olofsson
85ecd25268 Remving the ugly wait hack in the stimulus, not the way to drive the pipeline 2016-03-21 20:51:35 -04:00
Andreas Olofsson
3ae9c26d38 Changing shift/load order 
- Load should always have higher priority, but load is blocked if there is a pending shift anyway...
 2016-03-21 20:50:41 -04:00
Andreas Olofsson
a991a4fc06 Fixed mux bug in spi 
- copy paste error
 2016-03-21 20:49:39 -04:00
Andreas Olofsson
bc6641bcd0 Simplifying state machine on spi master 
- Divide and conquer, use the  par2ser wait signal to hold off on read
- Removed the stupid byte done state! Was too complicated.
 2016-03-21 20:48:18 -04:00
Andreas Olofsson
2a993815c3 Fixed readback bug 
- Only readback on reads
 2016-03-21 20:47:48 -04:00
Andreas Olofsson
71230c8c95 Resetting slave par2ser with ss (not nreset!) 
- Shifting out on positive edge of sclk
 2016-03-21 20:46:05 -04:00
Andreas Olofsson
7b3ca453f4 Looping back master spi access/packet to driver/stimulus 2016-03-21 20:27:10 -04:00
Andreas Olofsson
c9b2b9e0d8 Fixing basic spi test to fit new clock divider 2016-03-21 20:26:29 -04:00
Andreas Olofsson
b89f451c2f Fixing basic par2ser stall bug 
- don't start new transfer until current transfer is done
 2016-03-21 14:32:15 -04:00
Andreas Olofsson
1972fd21b6 Stressing pushback by removing the training wheels 
-Checks block with full throttle and with waits (for debug)
 2016-03-21 14:30:38 -04:00
Andreas Olofsson
d26d3efbc1 Fixing fifo status for mtx 
(signals were unconnected)
 2016-03-21 14:29:59 -04:00
Andreas Olofsson
29ae5b462b Adding mio test to stress fifo 
-pushback looks good!
 2016-03-21 14:29:03 -04:00
Andreas Olofsson
3175010236 MIO debug 
- fixing msbfirst packet mode bug
- fixing lsbfirst packet mode bug
- fixing clkphase writing bug
- changing default to msb first
- making a single DEF_CFG and DEF_CLK parameters (it was getting out of hand)
- improved test to do emode/amode testing, and writing to registers
-"amode" now works!!**
 2016-03-21 13:50:23 -04:00
Andreas Olofsson
87b502ba73 Changing transmit order for mtx_io 
-Making msbfirst the defaualt (looks cleaner on scope)
-Swapping bytes on msbfirst and ddr mode
-Implementing sdr mode on RX
 2016-03-21 13:48:57 -04:00
Andreas Olofsson
8709e0ff08 Adding decoding in MIO dut for register acess 
-no remote addresses should have bits 31:20 set to zero, so this seems like a safe hack for differentiating between data and control instructions
 2016-03-21 13:47:27 -04:00
Andreas Olofsson
18084bf63f MIO cleanup 
-adding target parameter to fifo
-fixing rx protocol bugs
-adding defaults to register file, usually these should be set to zero and
-don't clock gate the DDR TX, just causes output to toggle like clock, BAD!
-fixed status register sticky bug
-adding autoincrement feature in amode
-fixing dut file for new "mio" subsystem
-**emesh packet now goes through in loopback!!!**
 2016-03-21 11:27:35 -04:00
Andreas Olofsson
29aff43b59 Adding mio sub system module 
-Much easier to use and test, includes clockdiv and regs in one module
-Note that it's still possible to use the mio_dp raw if you tie off signals to constants and bring your own clock.
-Having both approachs should make everyone happy. Have found that SW developers usually can't write verilog and HW folks don't know C (so can't write to registers)...
 2016-03-21 11:25:33 -04:00