Andreas Olofsson
8f22ce2fec
Merge remote-tracking branch 'origin/elink_redesign_fred'
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Conflicts:
fpga/src/ecfg/hdl/ecfg.v
fpga/src/gpio/hdl/parallella_gpio_emio.v
2015-03-23 15:29:55 -04:00
Fred Huettig
857af62484
Partial integration of new elink
2015-01-28 13:53:09 -05:00
aolofsson
53f1ef0e46
Add register definition for ESYSDEBUG...
2014-12-12 12:20:18 -05:00
aolofsson
88443f7f98
Adding a read only debug register for monitor important elink signals.
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Useful for debugging new hardware.
2014-12-11 14:51:09 -05:00
Fred Huettig
ad8a088a36
eCfg: Renamed reset input to hw_reset, OR'd into ecfg_reset output.
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eCfg IP updated to match.
2014-11-19 16:59:04 -05:00
Fred Huettig
1bc118cfcd
Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign
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Conflicts:
fpga/src/ecfg/hdl/ecfg.v
2014-11-19 12:29:35 -05:00
Fred Huettig
440d932794
New Vivado-friendly modules, testbench for elink gold-vs-new.
2014-11-19 12:02:18 -05:00
aolofsson
26c5da0cbb
Create combined reset (hw+sw)
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Added data select output for axi_slave mux
Signal cleanup (gpio_data)
2014-11-06 11:52:38 -05:00
aolofsson
536613b230
Changed to 20 bit addressing for clarity in FPGA
2014-11-05 19:49:18 -05:00
aolofsson
4ab49e07c2
Reorganizing structure to be IP centric
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-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
2014-11-05 14:31:05 -05:00
