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47 Commits 7 Branches 1 Tag
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3 Commits

Author SHA1 Message Date
aolofsson
b83ef81db6 Wrong bus width (just cleanup..) 2014-12-15 15:26:07 -05:00
aolofsson
bb39314399 Verious silly compilation fixes, nothing to see here.. 2014-12-14 22:24:16 -05:00
aolofsson
4f51cc342d Adding new verilog modules for receiver and transmitter 
-moving away from Vivado block editor
-creating a "clean" split between RX and TX
 2014-12-14 17:18:53 -05:00