5 Commits

Author	SHA1	Message	Date
Andreas Olofsson	239ca128c2	Vivado run through ... -missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow	2015-04-08 23:40:16 -04:00
Andreas Olofsson	d2fc0da3a1	Fixing file permissions ... Verilog text files should not have execute permissions!	2015-04-08 13:26:12 -04:00
Andreas Olofsson	b0b9315bf1	Massive checkin... ... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)	2015-03-24 20:44:03 -04:00
Andreas Olofsson	230963ba6f	Integrating Fred's changes	2015-03-24 15:12:53 -04:00
aolofsson	2cb3b9a29b	Consolidating all axi interface in one directory ... Adding interface for axi lite slave, needs content	2014-12-14 22:22:49 -05:00