6 Commits

Author	SHA1	Message	Date
Andreas Olofsson	239ca128c2	Vivado run through ... -missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow	2015-04-08 23:40:16 -04:00
Andreas Olofsson	b0a94d7f43	Adding stubs for IP blocks used in elink	2015-04-08 23:38:36 -04:00
Andreas Olofsson	b0b9315bf1	Massive checkin... ... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)	2015-03-24 20:44:03 -04:00
Fred Huettig	573d322d16	Revert "Fixing port declarations (thanks Verilator!)" ... This reverts commit 75310447401bce8561b7a67d4c8aeca27c261464.	2015-01-28 14:15:13 -05:00
aolofsson	2c886c4e24	Fixing port declarations (thanks Verilator!)	2014-12-15 16:39:28 -05:00
aolofsson	47fa7ff23d	Adding stubs files for xilinx IP ... Goal is to create models for all of these	2014-12-14 22:21:01 -05:00