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Author SHA1 Message Date
Noah Moroze
b36d31290a Fix width of padring 'dout' ports 2021-07-06 17:51:24 -04:00
aolofsson
4556136e7b Removing depracated file 
-Power merged with domain
 2021-06-16 17:00:31 -04:00
aolofsson
7a136c39d8 Adding basic padring generator 2021-06-16 10:49:18 -04:00
aolofsson
bbc0e979d2 Whitespace cleanup to domains file 2021-06-16 09:33:13 -04:00
aolofsson
d6e18791b5 Adding place holder core power pad cell 2021-06-15 11:57:48 -04:00
aolofsson
403976b8c9 Adding corner pad place holder 2021-06-15 11:48:39 -04:00
aolofsson
3601fa409b Adding place-holder cell for padring 2021-06-15 11:45:10 -04:00
aolofsson
acc72c5762 Removing netlist directory 
-All abstracted information contained in hdl
 2021-05-26 14:57:25 -04:00
aolofsson
d0dab83075 Merging rtl and switch models in one verilog file 2021-05-25 19:27:00 -04:00
aolofsson
2eb3e4518b Prototype for driving cell level parameters 2021-05-25 16:10:50 -04:00
aolofsson
2e8551d468 Adding nor primitive circuit 2021-05-25 13:57:16 -04:00
aolofsson
b2624e803e Adding switch level modeling of nand gate 2021-05-25 13:48:00 -04:00
aolofsson
3fc3983494 Fixing concatentation errors 2021-05-24 20:56:48 -04:00
aolofsson
9631c50bae Adding scan cells to standard cell libs 2021-05-24 20:52:04 -04:00
aolofsson
f4184b048a Adding xor standard cell family 2021-05-24 20:30:20 -04:00
aolofsson
5e151efa51 Adding batch of oa/ao cells 2021-05-24 20:26:05 -04:00
aolofsson
a08ef0d84c Fixing nset typo 2021-05-24 20:25:55 -04:00
aolofsson
0489dd2d8c First batch of standard cells 2021-05-24 19:05:20 -04:00
aolofsson
a0625a7d0f Adding WIP/broken warning 2021-04-26 10:26:24 -04:00
aolofsson
3c6c41ff83 Removing depracated eda directory 2021-04-26 09:39:36 -04:00
Andreas Olofsson
3977791929
Merge pull request #108 from aolofsson/pr_aolofsson 
A long overdue merge of a private branch
 2021-04-26 08:58:44 -04:00
aolofsson
65a13b5067 Merge branch 'master' of github.com:aolofsson/private-oh into pr_aolofsson 2021-04-26 08:56:16 -04:00
aolofsson
ff4ddf28d8 Dummy commit 2021-04-26 08:44:21 -04:00
aolofsson
3911ad8c6e Using autoinst feature for fifo_sync 2021-04-18 22:30:13 -04:00
aolofsson
2ca5343322 Updating latch syntax to fix Foss parsing issues 2021-04-18 22:29:27 -04:00
aolofsson
413d1dec32 Addding full interface to memory 
-If you are going to instantiate a hard instance, you might as well do it right. For tools that generate these interfaces, who cares
-For debugging, nothing is worse than traversing an endless set of wrappers.
-Bigger interfaces are better than more levels
 2021-03-02 16:49:49 -05:00
aolofsson
9b63e23bda Adding always_latch to avoid verilator warnings 2021-03-02 16:49:20 -05:00
Andreas.Olofsson
1925c188c8 Fixing compilation error 2021-03-02 15:36:33 -05:00
Andreas.Olofsson
3e49fa499f Making almost full programmable in oh_fifo_sync 2020-12-07 16:58:47 -05:00
Andreas.Olofsson
401d1c2e93 Adding a generic single/dual/soft/hard memory macro 2020-12-04 15:58:53 -05:00
Andreas.Olofsson
490ce22244 Flattening memory hierarchy!!! 
-Now completely compatible with FPGA and ASIC flows with a single source
 2020-12-04 15:58:07 -05:00
Andreas.Olofsson
7ff50650f7 Changing name back to "oh_mem_dp" 
-Now moving to make the names the change, note that since there are many different designs within one SoC/compilation, you will need to have a large if-else somewhere on the design or an automated compiler for each project.
-I saw you have one file asic_mem that contains all the macros in the design with if-else statements inside
-Is there a situation where you would want to decide top what implementtaion you wnt.
-For example, you might want flip-flops sometimes, and other times perhaps a different aspect ratio?
-How to drive the floor-planning, by running experiments, not hard coding!!!
-A designer might want to choose (tall, wide, square, for hard macros)
-Also need to specify hard/soft on a per macro basis
 2020-12-04 12:39:45 -05:00
Andreas.Olofsson
b62c11cf67 name change from memory_sp to sram_sp 2020-11-02 15:01:50 -05:00
Andreas.Olofsson
022563c414 Name change for enoc packet to avoid signal confusion 2020-11-02 14:54:29 -05:00
Andreas.Olofsson
7b5e6a2380 MILESTONE: New enoc pack/unpack compiles! 2020-10-15 11:45:17 -04:00
Andreas.Olofsson
38cb339eda MILESTONE: New version of enoc command structure 2020-10-15 10:58:39 -04:00
Andreas.Olofsson
ed0f43a031 MILESTONE: Solidified enoc command decode 
-making IO memory mapped, should be invisible to user!
-don't push micro optimiation onto programmer!
-don't confuse user with implementation concerns, renaming input to input, output to output for packing!
 2020-10-15 10:19:34 -04:00
Andreas.Olofsson
046480bfb3 Adding enoc common opcode decode file 2020-10-15 10:12:40 -04:00
Andreas.Olofsson
798634a9c5 Renaming emesh as enoc (better description) 2020-10-15 09:38:12 -04:00
Andreas.Olofsson
f6b9f6cad7 Upating packet2emesh with new format. 
-Moving sa0/sa1 in order to simplify
-With the new clean format there is no need for the split
 2020-10-09 22:10:57 -04:00
Andreas.Olofsson
7c05557e6f MILESTONE: Yet another major revision of emesh protocol 
-Remove formats and rally around 16bit CMD,simplicty over optimization!
-Need to think of being scalable enough for 64bit memory and cache coherent systems!!!! The cost of this forward looking compatibility is only 8 bits, when compared to the 128 bits minimum of address/data pair, this is acceptable
 2020-10-09 21:54:33 -04:00
Andreas.Olofsson
558776a3b3 MILESTON: New packet format created for emesh 2020-10-09 13:18:03 -04:00
Andreas.Olofsson
8268480640 MILESTONE: Implemented new packet command 
-AW16 to AW128
 2020-10-07 10:36:37 -04:00
Andreas.Olofsson
0b91be7a75 New extended packet formats for emesh 2020-10-07 09:28:57 -04:00
Andreas.Olofsson
e123650d06 Major change of "wait" to "ready" 
-This will cause a lot of nasty bugs, but it's the right thing to do to be more consistent with standard buses going forward.
-Change is made from access/wait tp valid/ready
 2020-09-26 12:33:13 -04:00
Andreas.Olofsson
a3f08449e2 Simchecker printout fix 2020-09-26 12:32:38 -04:00
Andreas.Olofsson
58aabca0aa IOBUF name changes 
-Separating pullup and pulldown signals
-Changing direction of in/out names to avoid confusion
-direction is now with reference to the core
 2020-09-23 16:49:34 -04:00
Andreas.Olofsson
c215b48a55 Redesining oh_iddr 
-adding separate clock enables
-adding internal clock enable for neg edg sample
-combining q1/q2 legacy interfae into a single output
 2020-09-23 16:48:10 -04:00
Andreas.Olofsson
fda0f35dd9 Name change to packets 
-Using valid signal instead of access, more standardized
 2020-09-23 16:47:13 -04:00
Andreas.Olofsson
f817bb57ec Removing redundant code in async fifo instance 2020-09-23 16:46:46 -04:00