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22 Commits

Author SHA1 Message Date
Andreas Olofsson
3ce9b41726 Working mailbox!
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
2015-11-29 12:20:17 -05:00
Andreas Olofsson
0a2ea66b7e Bug fix. Adding missing ID parameter.
- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
61eb56c6f7 Final Vivado fixups:
- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
b6c95e5b94 Cleanup 2015-11-06 22:34:08 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
6114471935 Adding active signal to interface
- kind of like "pll lock"
2015-11-03 19:49:09 -05:00
Andreas Olofsson
028bf19382 TX clock and reset cleanup
- more modular
- two bits cominng from sys_clk elink config domain
- drives the tx and rx from top level elink
- from software you would probably write 2'b11 to reset both at same time
2015-10-07 19:15:29 -04:00
Andreas Olofsson
947a804c62 Making reset async
- making ecfg_elink reset only depend on por (otherwise chicken and egg)
-
2015-10-07 14:46:12 -04:00
Andreas Olofsson
415b8113df Adding proper "ETYPE" for wait signals
-single and diff should be fully supported
2015-09-27 08:40:36 -04:00
Andreas Olofsson
8b9ddb5d34 Hard coding for ephycard, may need to fix back later... 2015-09-25 15:21:21 -04:00
Andreas Olofsson
cfbbfeb574 Adding "ETYPE" as a parameter
-set to 0 for parallella
-set to 1 for ephycard
2015-09-14 22:03:22 -04:00
Patrik Lindström
5e8b10eafb Bug fixes
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
2015-08-24 22:50:28 +02:00
Patrik Lindström
f9c2a5abf3 moving idelay controller to eclocks.v
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
2015-08-24 21:08:49 +02:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Patrik Lindström
6d13611f21 script fixes 2015-06-30 16:02:39 +02:00
Patrik Lindström
667c7cb6a8 script fixes 2015-06-30 14:56:27 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
2015-05-19 22:07:16 -04:00
Andreas Olofsson
ab26378a99 Adding elink with axi interfaces 2015-05-09 08:52:55 -04:00