Andreas Olofsson
20534a6ed1
Added testmode to transmitter
...
-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
2015-05-01 17:47:24 -04:00
Andreas Olofsson
0ca303432b
Cleanup
2015-05-01 17:31:45 -04:00
Andreas Olofsson
e168bd5f98
reorg
2015-05-01 17:21:45 -04:00
Andreas Olofsson
0762b90fef
Reorg
2015-05-01 17:21:21 -04:00
Andreas Olofsson
5f15ed220d
Changing name
2015-05-01 14:42:15 -04:00
Andreas Olofsson
ad401d09e0
??
2015-04-30 23:35:01 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
...
Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
3ef05ad63a
Register map twiddling..
2015-04-28 17:00:17 -04:00
Andreas Olofsson
d00d58d116
Read response now a readable memory mapped register
...
Much better...hidden addresses SUCK!
2015-04-28 16:58:45 -04:00
Andreas Olofsson
2460aa9247
Bypass erx remap on all ID matches
...
Not just for read responses..
2015-04-28 16:58:05 -04:00
Andreas Olofsson
a6ac9b4666
Added bit to etx_remap
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-To enable writing to ERX, we need to include the group number
-support groups F,E,D,C (bits [19:18])
2015-04-28 16:56:31 -04:00
Andreas Olofsson
a2ceb8ff6e
Cleanup, two-link environment working
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-Write to config registers from RX path now working
2015-04-28 00:47:26 -04:00
Andreas Olofsson
02812c03a8
Fixing bug on 64 bit register write
2015-04-28 00:46:40 -04:00
Andreas Olofsson
0431d79992
Enabling RX always
...
-Should we ever turn this off?
2015-04-28 00:45:16 -04:00
Andreas Olofsson
96c35c4908
Removing filter for rxwr_access
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-Needed to enable simple mi_write interface on RX
2015-04-28 00:44:20 -04:00
Andreas Olofsson
f544c44a08
Adding register access from RX
...
-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
2015-04-27 23:51:00 -04:00
Andreas Olofsson
6b108f5e1f
Adding reset to synchronizer
...
(cause there may not be a clock...)
2015-04-27 16:03:57 -04:00
Andreas Olofsson
df53a2dc4f
Adding missing reset
2015-04-27 16:03:12 -04:00
Andreas Olofsson
a1722b7ae6
Adding timeout circuit
2015-04-27 16:02:15 -04:00
Andreas Olofsson
c9124f415b
Added "timeout" to elink interface
...
-Use as error interrupt?
-Is there another method for checking error?
2015-04-27 15:11:56 -04:00
Andreas Olofsson
b0116c9316
Added read watchdog timer
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-A read on transmit side initiates timer
-Timer is reset when read request comes back
(assumption last read requests starts timer..last return stops it)
2015-04-27 13:00:00 -04:00
Andreas Olofsson
3683c39e5b
Bug fix. Fifo read delay not accounted for
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-Added valid signal to fifo
2015-04-27 11:16:15 -04:00
Andreas Olofsson
4856e39193
RX address remap bug fix
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-Used the wrong sub vector...
(silly mistake)
2015-04-27 09:29:22 -04:00
Andreas Olofsson
d79447853f
Register name shuffle
2015-04-27 09:28:52 -04:00
Andreas Olofsson
3cb8d1d426
Adding test mode registers for transmit path
...
Makes it possible to easily test the IO path using the mi_ interface
The mi interface is very simple to drive in logic...
2015-04-27 00:04:30 -04:00
Andreas Olofsson
89286af8a9
Adding documentation of elink protocol
2015-04-26 23:02:13 -04:00
Andreas Olofsson
f7aef66f29
Bug fix: erx pipeline misalignment
...
-access signal happens one signal after empty goes low to compensate for fifo data latency
-verify that this is how the Xilinx FIFO works as well.
2015-04-26 08:31:36 -04:00
Andreas Olofsson
21f87edd87
Memory bug fix
...
-srcaddr (upper data of read response) was using input instead of output data
-blocking upper data on 32 bit reads and smaller (quieter..)
Need random DV to flush out these silly bugs...
2015-04-26 08:29:50 -04:00
Andreas Olofsson
afd6e86840
Fixing etx pipeline
...
-Fixed one bug inserted during edits, causing double transactions
-Added pipeline stall logic to all units
2015-04-25 23:28:52 -04:00
Andreas Olofsson
ca835b9607
tweaking register map again...
2015-04-25 23:28:18 -04:00
Andreas Olofsson
5f595a75d3
Register write bug for new map
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-Need to block access if [15] is one (reserved for emmurx)
2015-04-25 07:10:13 -04:00
Andreas Olofsson
919a5fa5e8
Register map twiddles
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-Fixed test to correspond to new map
2015-04-25 07:09:52 -04:00
Andreas Olofsson
c0d8c967c4
Address remapping integration
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Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
be42ea3b89
Register map change
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-Changed register map
-Splitting into groups, more natural
2015-04-24 17:38:01 -04:00
Andreas Olofsson
ea7683693c
Adding RX/TX address remapping
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The MMU is a monster and may be too much
Adding simple remapping modules
Covers todays feature and then some
1.) Static remapping
2.) Addresss compression
2015-04-24 17:29:05 -04:00
Andreas Olofsson
b25ad633f7
Readback cleanup
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RX/TX interfaces should be mininmized and standalone
Adding mux to consolidate to one "dout"
2015-04-24 17:27:35 -04:00
Andreas Olofsson
3b637e55f0
MILESTONE: Design once again passes test
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New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
0ed6afeac9
Added tag and group for read response
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-Still not sure about this..
2015-04-23 23:14:39 -04:00
Andreas Olofsson
46896c63ef
Bug fix, adding reset signal
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This will blocking when there is no clock at startup.
2015-04-23 23:13:05 -04:00
Andreas Olofsson
24fc91072d
Adding IDs to keep access signals straight
2015-04-23 23:11:58 -04:00
Andreas Olofsson
01fec0f72a
Fixed elink missind ID parameter
2015-04-23 20:07:52 -04:00
Andreas Olofsson
5c8fb41849
Fifo read bug
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-fifo should be read when it's not empty and there is no wait pushback
2015-04-23 20:07:10 -04:00
Andreas Olofsson
c4c1edc10f
Adding reset to critical signals in pipe
2015-04-23 20:06:11 -04:00
Andreas Olofsson
7ab3b3a8f8
Fixed floating net bug
2015-04-23 20:05:00 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3
Changing so basic elink unti is without AXI
2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f
Splitting register file into separate pieces
2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835
Changing to packet interface
2015-04-23 18:07:27 -04:00
