2 Commits

Author	SHA1	Message	Date
Andreas Olofsson	6e93d0399a	Hold hack.. ... -This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this. -Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV	2016-01-19 16:01:15 -05:00
Andreas Olofsson	cd624d6531	Adding IDDR model	2015-05-15 15:27:45 -04:00