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Author SHA1 Message Date
Andreas Olofsson
2672519ab0 Adding memory to driver 
-More modular, foudn myself adding memories in a lot of places
 2015-12-17 12:53:20 -05:00
Andreas Olofsson
167744d7a9 Fixed data width 2015-12-17 12:52:49 -05:00
Andreas Olofsson
5ddf9305a3 More packet interface changes... 2015-12-17 12:52:27 -05:00
Andreas Olofsson
d558bd5f99 Packet converter interface changes 
-packet2emesh and emesh2packet had interface name changes
 2015-12-17 12:51:22 -05:00
Andreas Olofsson
dbd8cd8044 Adding common module for write alignment 2015-12-17 12:37:41 -05:00
Andreas Olofsson
79c312d166 Cleanup 2015-12-17 12:36:02 -05:00
Andreas Olofsson
3708417934 Reuse refactoring 
-Made AW primary parameter to make reuse possible with other design
-Insert TARGET_SIM ifdef to make design synthesizable
 2015-12-17 12:34:32 -05:00
Andreas Olofsson
27d7b0ed7c Cleaning up code 2015-12-17 12:34:03 -05:00
Andreas Olofsson
2a70178f47 Changing core parameter of packets 
-Address width is a more natural primary component
 2015-12-17 12:33:19 -05:00
Andreas Olofsson
ec627556f7 Fixing basic FIFO bug 
- count was not fully reset...
- adding parameter values to memory instance
 2015-12-10 19:32:15 -05:00
Andreas Olofsson
22976b781d Adding count/almost full to fifo 2015-12-08 21:10:17 -05:00
Andreas Olofsson
71b467728d Making mux parametrized 2015-12-07 11:19:12 -05:00
Andreas Olofsson
dd811ab417 Fixing unconnected wire bug 2015-12-05 09:01:18 -05:00
Andreas Olofsson
2d953d5639 Fixed unconnected wires in standby circuit 2015-12-04 17:32:15 -05:00
Andreas Olofsson
51fb4ad4a4 Changing memory parameter to DEPTH 2015-12-04 03:38:51 -05:00
Andreas Olofsson
f5bb42dfe3 Moving axi cells to own folder 2015-12-04 03:38:26 -05:00
Andreas Olofsson
d5edb1ca88 Fixing priority on etx_arbiter 
- don't do a combinatorial loopback on wait in a primitive cell, just bad practice...
- changed priority to give readback priority over read, safer?
 2015-12-04 03:36:42 -05:00
Andreas Olofsson
de012ec9c8 Changes to oh common modules 
- Converting some modules to be more ASIC friendly
 2015-12-04 03:12:07 -05:00
Andreas Olofsson
eb8f6c1f51 Adding datagate power saving module 2015-12-03 18:05:08 -05:00
Andreas Olofsson
8464c3dcb0 Adding standby logic block 2015-12-03 18:04:46 -05:00
Andreas Olofsson
16b0655151 Name change for arbiter 2015-12-03 18:04:10 -05:00
Andreas Olofsson
b9107474a9 Vectorizing oh_clockgate 2015-12-03 18:03:02 -05:00
Andreas Olofsson
69d2c2c5fb Prettyfying csa port names 2015-12-03 18:01:47 -05:00
Andreas Olofsson
3a8f81d4a3 Changing single port memory to be ASIC friendly 2015-12-03 18:01:21 -05:00
Andreas Olofsson
7b8460b145 Fixing up issues with database reorg 
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
 2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9 Massive reorganization to impove reuse 
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
 2015-11-30 13:45:49 -05:00
Andreas Olofsson
44bbaeb830 Fixed typo on MMU lookup. 
-MMU now seems to work...
 2015-11-29 19:10:46 -05:00
Andreas Olofsson
ddfeebd33f Cleaning up read response logic 
- Bypass path was ugly! Always try to go through the same logic path as much as possible.
- Note: when MMU is enabled, you need to put in entry for read return (ie 810)
 2015-11-29 19:07:28 -05:00
Andreas Olofsson
082593b2e9 Adding tests for mmu and remapping logic 2015-11-29 19:06:31 -05:00
Andreas Olofsson
7e49b29a79 Moving tests for idelay, mailbox, timeout from epiphany-examples 
-Idea is to create complete packages
-All hardware modules should be complete, separation of tasks/sources can drive 10x in dev cost.
 2015-11-29 12:44:22 -05:00
Andreas Olofsson
b58ceef19c Merge branch 'master' of https://github.com/parallella/oh 2015-11-29 12:42:24 -05:00
Andreas Olofsson
9ddd71024d Fixing system_bd interface for "mailbox_irq" signal 2015-11-29 12:41:53 -05:00
Andreas Olofsson
3ce9b41726 Working mailbox! 
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
 2015-11-29 12:20:17 -05:00
Andreas Olofsson
711088a9e7 Fixed mailbox bug on remap 
- Bypassing remap on write to RX registers
- Otherwise the write to mailbox gets dropped since 810 gets remapped to 310
 2015-11-29 12:10:53 -05:00
Andreas Olofsson
13005e6cbf Updated mailbox test 
- Added mailbox status address
- Moved mailbox registers
 2015-11-29 12:09:47 -05:00
Andreas Olofsson
03473c393f Merge pull request #22 from peteasa/AddMakefiles 
Added Makefiles to make build easier
 2015-11-29 11:23:43 -05:00
Andreas Olofsson
2ca649394b Adding timeout response code 2015-11-29 10:27:43 -05:00
Peter Saunderson
889b24d72e Added Makefiles to make build easier 
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2015-11-29 14:44:21 +00:00
Andreas Olofsson
ad568ad0a0 Implementing simple 64K cycle timeout for slave interface 2015-11-28 22:31:39 -05:00
Andreas Olofsson
099dbececa Adding test for mailbox readback 2015-11-28 21:42:05 -05:00
Andreas Olofsson
c294ba7775 Fixing readback from mailbox 2015-11-28 21:41:18 -05:00
Andreas Olofsson
0fc4b6188a Test cleanup 
- added lint script using verilator
- adding verilator filter commands for fifo behavioral
- Longer pushbacks in ememory
 2015-11-28 20:15:06 -05:00
Andreas Olofsson
0b6f7f7efb Making wait default 0 2015-11-28 20:13:47 -05:00
Andreas Olofsson
1890657d6d Solved read response bug. MATMUL WORKS!!!! 
- Turns out I was debugging ghosts for ~1 day today. Everything was working in simulation but nothing works in the FPGA. Since I was only changing small logic stuff, I didn't bother checking the warning messages in Viviado. Turns out for some reason it was throwing away some logic and disconnecting all the important rr signals
- This is where I was making changes, but I still can't figure out what exactly was happening...doesn't make sense. Either there is a bug in icarus or in vivado, this shouldn't happen!
 2015-11-25 23:50:29 -05:00
Andreas Olofsson
08f5d28ed4 Test cleanup 2015-11-25 23:49:56 -05:00
Andreas Olofsson
8856f7c763 DV cleanup 2015-11-25 22:00:07 -05:00
Andreas Olofsson
045652cc10 Adding TXPACKET register to doc 2015-11-25 21:59:43 -05:00
Andreas Olofsson
d66317abbc Fixing bug for readback?? 
- There was definitely a bug there, that has been fixed
- But now the interface seems completely broken...
- Passes in simulation and "should work"...
 2015-11-25 21:57:25 -05:00
Andreas Olofsson
379099da9c Filtering register write transactions 
-They were going out on the elink (not safe)
 2015-11-25 21:56:56 -05:00
Andreas Olofsson
33d5fb72e1 Filtering out short wait-low pulses from legacy elink 
-Feels safer, should not be any short wait glitches
 2015-11-25 21:55:37 -05:00