FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
1,060 Commits 7 Branches 1 Tag
Commit Graph

1060 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andreas Olofsson
29ae5b462b Adding mio test to stress fifo 
-pushback looks good!
 2016-03-21 14:29:03 -04:00
Andreas Olofsson
3175010236 MIO debug 
- fixing msbfirst packet mode bug
- fixing lsbfirst packet mode bug
- fixing clkphase writing bug
- changing default to msb first
- making a single DEF_CFG and DEF_CLK parameters (it was getting out of hand)
- improved test to do emode/amode testing, and writing to registers
-"amode" now works!!**
 2016-03-21 13:50:23 -04:00
Andreas Olofsson
87b502ba73 Changing transmit order for mtx_io 
-Making msbfirst the defaualt (looks cleaner on scope)
-Swapping bytes on msbfirst and ddr mode
-Implementing sdr mode on RX
 2016-03-21 13:48:57 -04:00
Andreas Olofsson
8709e0ff08 Adding decoding in MIO dut for register acess 
-no remote addresses should have bits 31:20 set to zero, so this seems like a safe hack for differentiating between data and control instructions
 2016-03-21 13:47:27 -04:00
Andreas Olofsson
18084bf63f MIO cleanup 
-adding target parameter to fifo
-fixing rx protocol bugs
-adding defaults to register file, usually these should be set to zero and
-don't clock gate the DDR TX, just causes output to toggle like clock, BAD!
-fixed status register sticky bug
-adding autoincrement feature in amode
-fixing dut file for new "mio" subsystem
-**emesh packet now goes through in loopback!!!**
 2016-03-21 11:27:35 -04:00
Andreas Olofsson
29aff43b59 Adding mio sub system module 
-Much easier to use and test, includes clockdiv and regs in one module
-Note that it's still possible to use the mio_dp raw if you tie off signals to constants and bring your own clock.
-Having both approachs should make everyone happy. Have found that SW developers usually can't write verilog and HW folks don't know C (so can't write to registers)...
 2016-03-21 11:25:33 -04:00
Andreas Olofsson
dc51ad3935 Adding mio-->emesh interface 
-Select between autoincrement mode and pass through mode with "amode"
 2016-03-21 11:25:03 -04:00
Andreas Olofsson
8633b09de2 Adding constant for mio 
-Not sure the order works here...
 2016-03-21 11:24:19 -04:00
Andreas Olofsson
a2aa5e8b5b Changing CONFIG bitfield in MIO 2016-03-21 11:23:25 -04:00
Andreas Olofsson
35f74f615f Adding build_all script 
-So many modules depend on each other, so you need to ability to compile all when you make a change to a core module
 2016-03-21 11:22:24 -04:00
Andreas Olofsson
7f0491d206 Cleaning up GPIO 
- AW parameter was missing in p2e
- Blocking input data with input enable (alsom done at io pad)
 2016-03-21 11:20:59 -04:00
Andreas Olofsson
93154c38f8 Adding special div2 logic for clock divider 
- Using negedge of clock for phase shifting 2nd clock by 90 degrees. Used by elink and mio
 2016-03-21 11:19:25 -04:00
Andreas Olofsson
3fa5fce86f Cleaning up fifos 
- Making default parameter generic (will need to fix elink next..)
- Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
 2016-03-21 11:18:07 -04:00
Andreas Olofsson
b61d55533e Fixing par2ser bugs 
-access out signal was broken (may need to fix again for spi)
-lsbfirst mode was broken
-made datasize 8 bits at interface
 2016-03-21 11:16:42 -04:00
Andreas Olofsson
490a3f6be1 SPI compilation cleanup 
- due to changes in par2ser and clock divider
- disadvantage of using common modules that change...
 2016-03-21 11:15:41 -04:00
Andreas Olofsson
fec6a98d90 Refactoring mio 
- changing datapath name to mio_dp (new methodology)
- top level should be complete block (with control + clock) for ease uf use
- clock renaming
 2016-03-21 06:15:50 -04:00
Andreas Olofsson
5b799de0eb Augmenting dv for mio 
- now includes mio regs as well
- next: create a complete block, ie dog fooding to include the mio_regs an axi interface, and a decoder interface to make it look like a subsystem (like the elink)
 2016-03-20 22:40:36 -04:00
Andreas Olofsson
5edf209983 New MIO integration 
- removing tx protocol block (reduces to par2ser)
- adding status bits to interface
- adding control signals from mio_regs
 2016-03-20 22:39:22 -04:00
Andreas Olofsson
5ff50f78c0 Fixing mtx io logic 
- adding support for single data rate
- removing wait logic from io registers, should only go to fifo
 2016-03-20 22:37:50 -04:00
Andreas Olofsson
d800325f50 Reformatting to use "N" as the main parameters 
-simpler..
 2016-03-20 22:37:30 -04:00
Andreas Olofsson
308b46366a Refactoring rx to use ser2par block 2016-03-20 22:36:33 -04:00
Andreas Olofsson
c18177c8a7 Adding register 
- These can be used to make the configuration of the mio datapath programmable
- This is what I should have done for the elink. Always separate the control from the datapath!!
 2016-03-20 22:35:43 -04:00
Andreas Olofsson
f6f1009b52 Removing protocol block, redundant 2016-03-20 22:35:30 -04:00
Andreas Olofsson
d1fd144374 New and improved MIO interface 2016-03-20 22:33:57 -04:00
Andreas Olofsson
e5a8227509 Adding features to clock divider 
-splitting out period from phase
-adding a second phase shifted clock (running off one counter)
-adding orthogonal control of rising and falling edge
 2016-03-20 18:17:26 -04:00
Andreas Olofsson
015b969ac2 Making default parameter N=1 for muxes 
- Less reconfiguring of parameters at instantiation time
 2016-03-17 23:41:56 -04:00
Andreas Olofsson
e36a817846 Fixing link script 2016-03-13 09:31:45 -04:00
Andreas Olofsson
4b1372eb3b Implementing GPIO readback circuit 
-added test, looks good
-reduced decoder width to 16 regs (seems reasonable for gpio)
 2016-03-13 09:28:17 -04:00
Andreas Olofsson
4517280e45 Adding emesh readback circuit 2016-03-13 09:27:39 -04:00
Andreas Olofsson
a8182de5e1 Adding environment setup script 2016-03-12 16:49:56 -05:00
Andreas Olofsson
74d1a9dc72 Fixing SPI header file inclusion issue 2016-03-11 15:08:01 -05:00
Andreas Olofsson
56ed1626b5 SPI working! 
-changed register file sampling to falling edge of sclk...ran out of edges
-fixed the register map for readback
-fixed status register
-fixed user register decode
 2016-03-10 22:04:24 -05:00
Andreas Olofsson
871da0488e Completed readback circuit on master 2016-03-10 22:03:38 -05:00
Andreas Olofsson
b34a3795e8 Completed basic SPI test 
- configure master
- write to tx fifo
- read from remote slave
- read from local master register
 2016-03-10 22:02:25 -05:00
Andreas Olofsson
a7003be8e9 Changing SPI command structure 
- Read/write commands should be at MSBs (7:6)
- Fixed fifo read race..need to look at this again
 2016-03-10 17:33:52 -05:00
Andreas Olofsson
3ca89dca2b Fixed serializer bug 
- ..hopefully last one
- incorrect stall signal made transactions get lost
 2016-03-10 17:33:02 -05:00
Andreas Olofsson
ed8d29ee2c Fixing serializer bug 
- SPI now working...
 2016-03-10 17:03:38 -05:00
Andreas Olofsson
da6856befa Adding reset signal to pulse interfaces 
- Needed for some logic with feedback, otherwise you get "x" loop
- Those who don't need it should be able to connect nrest to 1'b1
 2016-03-10 17:02:03 -05:00
Andreas Olofsson
286914e53c SPI debug cleanup 2016-03-10 17:01:29 -05:00
Andreas Olofsson
534fa69b50 Fixing SPI slave write register bug 
- Writes working
 2016-03-10 17:00:52 -05:00
Andreas Olofsson
f9414d91ee Changin SPI slave parameter 
- More natural to work with UREGS
 2016-03-10 17:00:13 -05:00
Andreas Olofsson
af96108db1 Fixing SPI bugs 
- Now working with byte addresses
- Wait should be on prog_full
 2016-03-10 16:58:18 -05:00
Andreas Olofsson
4589062821 Fixing SPI pushback contention bug (typo) 2016-03-10 16:57:37 -05:00
Andreas Olofsson
383dd50b99 Fixed lethal off by one fifo full bug! 2016-03-10 14:58:29 -05:00
Andreas Olofsson
63b56d9ec9 Adding command reg to spi master 
- Makes the emode more efficient, only setup command once
 2016-03-10 14:20:25 -05:00
Andreas Olofsson
8cf7c40c44 Simplifying spi slave 
- Clock sync made easier by detecting rising edge of ss
- Piping data into slave regs
- State machine simplified
 2016-03-10 14:19:07 -05:00
Andreas Olofsson
d57306619b Adding SPI documentation 2016-03-10 14:17:50 -05:00
Andreas Olofsson
6ad31e5c20 Cleanup GPIO docs table 2016-03-10 14:17:33 -05:00
Andreas Olofsson
e08f5a8fc7 Adding address table to GPIO 2016-03-10 11:13:24 -05:00
Andreas Olofsson
41e789b677 Refactoring to maximize code reuse 
-using common clock divider, ser2par block
-starting the readbkack circuit + auto transfer
 2016-03-10 11:07:51 -05:00