Andreas Olofsson
0437727d94
Adding new clocks to interface
2016-02-26 17:14:23 -05:00
Andreas Olofsson
3fc14dd0c1
Moving to "config" for IP
...
-Need to supply a config constant file at command line
(not with "include")
2016-02-26 17:13:20 -05:00
Andreas Olofsson
26474a40a7
Changed include file to ".vh"
2016-02-26 17:02:59 -05:00
Andreas Olofsson
67afb87881
Cleaning up sp memory changes
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-removing incorrect bist dout port
-repair vector name change
2016-02-26 17:01:24 -05:00
Andreas Olofsson
a4f4881ccf
Adapting ememory to new single port memory interface
2016-02-26 16:59:41 -05:00
Andreas Olofsson
4a94d45750
Creating new "CLKDIV" module
...
-Model should be separate from design (very different needs)
2016-02-26 16:56:56 -05:00
Andreas Olofsson
d0171fd1d8
Adding ASIC interface to single port memory
...
- Yes, I know this means more signals for others to "ignore". The fpga way to handle this is to auto generate hierarchy to hide the signals.
- I prefer a flatter structure with signals tied off and a library of known good components in a repo!
2016-02-26 16:31:09 -05:00
Andreas Olofsson
c9e5336b5a
Formatting
2016-02-25 20:05:49 -05:00
Andreas Olofsson
090b6286d9
Wideneded scope of readme
2016-02-25 20:04:39 -05:00
Andreas Olofsson
5f9fea960a
Changing interface for consistency
...
-simple functions should strive for "in" and "out" parameters
2016-02-25 15:02:53 -05:00
Andreas Olofsson
1c0646c569
Implemented absolute value function
2016-02-25 15:00:33 -05:00
Andreas Olofsson
39f8115df8
Adding bitreverse module
2016-02-25 14:50:43 -05:00
Andreas Olofsson
701b1deca3
Bug fix: adding missing event on reset
2016-02-25 14:43:00 -05:00
Andreas Olofsson
4900f2c6e2
Propagating clock during reset
2016-02-25 14:42:39 -05:00
Andreas Olofsson
2a22cd6ff8
Removing delay + clock gating
...
- delay could hide bad designs..
- clock gating was hard to handle from outside
2016-02-25 14:41:30 -05:00
Andreas Olofsson
8f37435d95
Instantiating parallel CRC calculators
2016-02-25 14:40:38 -05:00
Andreas Olofsson
1fa1e05754
Adding parallel CRC generators from @alexforencich
2016-02-25 14:40:02 -05:00
Andreas Olofsson
87848d5a14
Parity operator
2016-02-25 10:56:35 -05:00
Andreas Olofsson
096dd728e4
Adding c2c description
2016-02-24 20:57:55 -05:00
Andreas Olofsson
387841bebd
Update README.md
2016-02-24 20:48:04 -05:00
Andreas Olofsson
dca2060895
Adding README file
2016-02-24 20:44:06 -05:00
Andreas Olofsson
96772b15f0
Adding new simplel chip to chip link
2016-02-24 20:29:56 -05:00
Andreas Olofsson
ddfb4e00de
Fixing generic fifo
...
- This one is looking better
- Still needs more review. At least now it has a testbench...
2016-02-24 14:26:25 -05:00
Andreas Olofsson
ea2ee15d5c
Only run clock divider if enabled
2016-02-24 14:25:53 -05:00
Andreas Olofsson
d246529b4b
Fixing sampling bug
2016-02-24 14:25:23 -05:00
Andreas Olofsson
cdef6141b4
Adding 2nd clock to interface
...
- Randomizeing clock frequencies
- Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...)
- Don't be clever, be smart!
2016-02-24 14:23:30 -05:00
Andreas Olofsson
117a4fee0d
Doing forall "dut*.v"
...
- Adding entries to a list gets old real fast....
2016-02-24 14:22:32 -05:00
Andreas Olofsson
fc7dc0e70a
Adding "SEED" as basic parameter
...
-making randomness clocks a first class citizen
-Verilog doesn't have a seed, need to drive it from the shell
-a must for async clocks, useful for many things
-does not preclude randomization externally as well
2016-02-24 14:21:04 -05:00
Andreas Olofsson
bb4a602f7f
New "dut files"
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- new clocks (clk1 and 2)
- simpler names
- fifo dut
2016-02-24 14:19:57 -05:00
Andreas Olofsson
c9601a8f9c
Adding clk90 output to clkdiv
...
-Added testbench
-Needs more review!
2016-02-23 17:49:08 -05:00
Andreas Olofsson
84490be604
Adding testbench for clockdiv and gray converter
2016-02-23 17:17:41 -05:00
Andreas Olofsson
be22598935
Adding basic unit wiggle tests
2016-02-23 17:17:05 -05:00
Andreas Olofsson
852d7da490
Adding generic target
...
- all sims should have a "cfg file"
- since everything is configurable, this is the easiest way
2016-02-23 15:44:31 -05:00
Andreas Olofsson
5c66c16714
Reorg: moving generic fifo to separate file
...
- design was too "xilinx centric" before.
- library should work in any technology
2016-02-23 15:43:28 -05:00
Andreas Olofsson
91c662e528
Adding experimental fifo circuit
...
-not debugged
2016-02-23 15:42:55 -05:00
Andreas Olofsson
71efa8669f
Fixing new ddr circuits
2016-02-23 15:42:32 -05:00
Andreas Olofsson
98a14099ca
Fixing basic counter
2016-02-23 15:41:35 -05:00
Andreas Olofsson
8e466f3137
Adding debouncer circuit
2016-02-23 15:41:18 -05:00
Andreas Olofsson
758f5e6763
Ignoring .bin files
2016-02-23 15:40:07 -05:00
Andreas Olofsson
643c48b6e1
Merge branch 'master' of github.com:parallella/oh
2016-02-22 23:50:58 -05:00
Andreas Olofsson
c88bcb303e
Adding regmap for pic
2016-02-22 23:50:37 -05:00
Andreas Olofsson
e051d7d516
Adding vectorized iddr/oddr cells
2016-02-22 23:47:27 -05:00
Andreas Olofsson
199369e344
Merge pull request #52 from abdullahyildiz/master
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Added the definitions of priority encoder and lookup table
2016-02-21 13:25:24 -05:00
Andreas Olofsson
3421e89536
Renaming irqc to pic
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-More attractive name (has a wiki entry even...)
2016-02-20 21:55:49 -05:00
abdullah
de9f664cc0
Added the definition of lookup table
2016-02-19 22:38:49 +02:00
abdullah
bfe596a9a9
Merge pull request #1 from abdullahyildiz/abdullahyildiz-patch-1
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Added the definition of priority encoder
2016-02-19 22:28:27 +02:00
abdullah
5bc9198436
Added the definition of priority encoder
2016-02-19 22:27:52 +02:00
Andreas Olofsson
c2d74628ea
Merge pull request #51 from Idorobots/patch-1
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Fixed some typos in the glossary
2016-02-19 08:28:53 -05:00
Kajetan Rzepecki
60fe4c73e4
Fixed some typos in the glossary
...
And now I'm off to Wikipedia! :)
2016-02-19 14:24:09 +01:00
Andreas Olofsson
1c88992d64
Adding coding methodology link
2016-02-18 17:06:01 -05:00
