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Author SHA1 Message Date
Andreas Olofsson
e033e233d0 Integrating emesh memory module 
-This will flush out the final read response path
 2015-04-20 23:07:13 -04:00
Andreas Olofsson
6a6f953986 Adding emesh memory module (empty for now) 2015-04-20 23:06:49 -04:00
Andreas Olofsson
4c44c59079 Message box working... 
-More testing needed!
 2015-04-19 21:55:07 -04:00
Andreas Olofsson
7e44dfc84c Memory read bug (clk floating) 2015-04-19 21:54:22 -04:00
Andreas Olofsson
6cc5d6de90 MMU working... 
-Needs more testing
 2015-04-19 21:36:47 -04:00
Andreas Olofsson
7c93c565e9 Adding back awid, arid, lock to AXI interface 2015-04-18 17:35:22 -04:00
Andreas Olofsson
44a4d0e669 Adding gtkwave signals file 2015-04-18 16:42:34 -04:00
Andreas Olofsson
9e931c47ec Cleanup 2015-04-18 16:26:32 -04:00
Andreas Olofsson
f141a0e320 Clock cleanup 
-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
 2015-04-18 16:24:26 -04:00
Andreas Olofsson
b30dbe6005 Fixed to fit with new register map 2015-04-18 16:23:35 -04:00
Andreas Olofsson
00a921b839 Changed register map 
-Moved "groups" to E,D,C
-Changed names to EL* (shorter is better, clear enough)
-Moved order to fit logical operation during init
-Moved embox registers to MMR group
DONE!
 2015-04-18 16:21:45 -04:00
Andreas Olofsson
27087fb736 ESAXI cleanup 
-widen address bus to 32 bits
-blocking access to elink on ecfg access
-fixing decoding for embox
 2015-04-18 16:18:41 -04:00
Andreas Olofsson
baf6cc5a62 Removed synchronizer on TXLCLK 2015-04-18 16:17:44 -04:00
Andreas Olofsson
643ceed432 Adding manual test feature to testbench 
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
 2015-04-18 16:14:53 -04:00
Andreas Olofsson
8adc060bc8 Clock divider fixup 
-changed to latest and hopefully final register config
-fixed functional bugs (was broken..)
-added xor for sensing change of clock frequency
 2015-04-18 16:12:43 -04:00
Andreas Olofsson
80bb50703b Adding basic elink read/write test 2015-04-18 16:12:04 -04:00
Andreas Olofsson
f606fc5794 Adding high level single ported memory 2015-04-18 16:11:21 -04:00
Andreas Olofsson
9c24869d72 Simplifying register names 2015-04-18 09:49:54 -04:00
Andreas Olofsson
3c2b760a2f Prettifying format..starting to look decent 2015-04-18 07:51:13 -04:00
Andreas Olofsson
47bf283f05 Adding experimental README file 2015-04-18 07:39:38 -04:00
Andreas Olofsson
85db5d9de0 Spell checking comments 
First time ever using spell cheker in EMACS. Hard to believe...but it's true!
I am sure this speaks volume for how little I have commented my code over the years!
 2015-04-18 06:36:33 -04:00
Andreas Olofsson
c41a0a8640 Cleaning up licenses for consistency 
-All files still GPLv3
-Placed at the bottom of the file (I am tired of looking at them!)
 2015-04-17 22:21:08 -04:00
Andreas Olofsson
18b2c489b0 Adding documentation to elink top level module 2015-04-17 22:10:14 -04:00
Andreas Olofsson
4c06e4be61 Changed stimulus format to 32b_32b_32b_8b 
Format is:

srcaddr_data_dstaddr_{ctrlmode,datamode,write,access}
 2015-04-17 16:02:23 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
7bc3b662ab Added profull HACK to async_fifo 
-this module needs rework
-needs to have same capabilities as standard FPGA async fifos
-remove this later
 2015-04-17 15:49:58 -04:00
Andreas Olofsson
9f2cbb64cb Fixed odd/even copy past bug on DDR sampler 2015-04-17 15:49:01 -04:00
Andreas Olofsson
bd90cc8f92 Fixed testbench bug (copy paste, RX not enabled)... 2015-04-17 10:08:17 -04:00
Andreas Olofsson
dca611c5ba Getting all the clk config numbers aligned 
Not changing these again!!
 2015-04-16 22:48:31 -04:00
Andreas Olofsson
068d63279b Changing ESYSCLK definition (again.....) 
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
 2015-04-16 22:31:36 -04:00
Andreas Olofsson
c4d5381c8f Added serial to parallel circuit + Xilinx BUFR 2015-04-16 22:30:09 -04:00
Andreas Olofsson
dcdf4a9231 Adding experimental OSERDESE2 model 
Experimental model, dirty design
Bits are coming out and frame looks good..
Will continue with RX and debugging tomorrow
 2015-04-15 23:03:33 -04:00
Andreas Olofsson
b1a9f502ca Xilinx models 
-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench
 2015-04-15 17:54:19 -04:00
Andreas Olofsson
bdec6c1067 Cleaning up tx config register 2015-04-15 17:53:50 -04:00
Andreas Olofsson
846bfa3357 Fixing startup issues in transmit path: 
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
 2015-04-15 16:33:20 -04:00
Andreas Olofsson
710c48b880 Fixed clock divider circuit 
-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff
 2015-04-15 14:56:29 -04:00
Andreas Olofsson
69f3df4140 Continued work to create clean design: 
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
 2015-04-15 11:54:43 -04:00
Andreas Olofsson
bee90fcacc Support files for fifo 2015-04-14 23:56:59 -04:00
Andreas Olofsson
4fd4c8e989 Adding platform agnostic dual ported memory and async fifo 2015-04-14 23:56:00 -04:00
Andreas Olofsson
3ddb6679ff Silly bug in access logic 
Looks like I was interrupt while coding..
 2015-04-14 23:55:00 -04:00
Andreas Olofsson
67f242c8ef Running with "TARGET_CLEAN" 2015-04-14 23:48:58 -04:00
Andreas Olofsson
b58660e9a6 Adding different data modes 
Good enough fufu testing...
..the next step is driving stimulus with transactor through Verilator..
 2015-04-14 23:47:49 -04:00
Andreas Olofsson
04c65d3570 Adding back the "common" directory 2015-04-14 23:22:29 -04:00
Andreas Olofsson
93330039e0 AXI bug fixes 
-First bug was a typo. Cursing AXI for making every signal look exactly the same at first glance.  Not good use practice
-Second bug was sloppy. (removed pipeline stage on write data by mistake)
 2015-04-14 20:26:58 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup 
~10 real bugs
-mostly name mismatches and bit range mistakes
 2015-04-14 14:00:23 -04:00
Andreas Olofsson
f33d940df8 Fixed renaming bug..axi ready signal not working 
(would have been caught by verilator, time to lint...)
 2015-04-14 13:08:27 -04:00
Andreas Olofsson
bf1671b1e9 Added "fufu" DV environment for elink 
-Icarus for now, verilator comes next
-Using our "standard" emesh interface
..here we go...
 2015-04-14 11:45:33 -04:00
Andreas Olofsson
d809f46286 Removing unused signals from interface 2015-04-14 11:44:31 -04:00
Andreas Olofsson
084f630c4e Adding missing stubs 2015-04-14 09:42:19 -04:00
Andreas Olofsson
b4c5ef302b Adding fifo wrapper 2015-04-14 09:06:08 -04:00