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1,373 Commits 7 Branches 1 Tag
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159 Commits

Author SHA1 Message Date
Andreas.Olofsson
7bd980fca2 Adding include directorys to lib.cmd 2020-02-01 09:07:47 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
a6f1dc8971 Merge branch 'master' of github.com:parallella/oh 2016-03-22 08:01:04 -04:00
Andreas Olofsson
85ecd25268 Remving the ugly wait hack in the stimulus, not the way to drive the pipeline 2016-03-21 20:51:35 -04:00
Andreas Olofsson
3ae9c26d38 Changing shift/load order 
- Load should always have higher priority, but load is blocked if there is a pending shift anyway...
 2016-03-21 20:50:41 -04:00
Andreas Olofsson
b89f451c2f Fixing basic par2ser stall bug 
- don't start new transfer until current transfer is done
 2016-03-21 14:32:15 -04:00
Andreas Olofsson
93154c38f8 Adding special div2 logic for clock divider 
- Using negedge of clock for phase shifting 2nd clock by 90 degrees. Used by elink and mio
 2016-03-21 11:19:25 -04:00
Andreas Olofsson
3fa5fce86f Cleaning up fifos 
- Making default parameter generic (will need to fix elink next..)
- Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
 2016-03-21 11:18:07 -04:00
Andreas Olofsson
b61d55533e Fixing par2ser bugs 
-access out signal was broken (may need to fix again for spi)
-lsbfirst mode was broken
-made datasize 8 bits at interface
 2016-03-21 11:16:42 -04:00
Andreas Olofsson
e5a8227509 Adding features to clock divider 
-splitting out period from phase
-adding a second phase shifted clock (running off one counter)
-adding orthogonal control of rising and falling edge
 2016-03-20 18:17:26 -04:00
Andreas Olofsson
015b969ac2 Making default parameter N=1 for muxes 
- Less reconfiguring of parameters at instantiation time
 2016-03-17 23:41:56 -04:00
Andreas Olofsson
4d172960c1 Renaming the generic dut template file 2016-03-11 16:40:30 -05:00
Andreas Olofsson
e1f8b1d6c4 Adding dummy dut to make autocomplete work in emacs 2016-03-11 16:38:17 -05:00
Andreas Olofsson
3ca89dca2b Fixed serializer bug 
- ..hopefully last one
- incorrect stall signal made transactions get lost
 2016-03-10 17:33:02 -05:00
Andreas Olofsson
ed8d29ee2c Fixing serializer bug 
- SPI now working...
 2016-03-10 17:03:38 -05:00
Andreas Olofsson
da6856befa Adding reset signal to pulse interfaces 
- Needed for some logic with feedback, otherwise you get "x" loop
- Those who don't need it should be able to connect nrest to 1'b1
 2016-03-10 17:02:03 -05:00
Andreas Olofsson
383dd50b99 Fixed lethal off by one fifo full bug! 2016-03-10 14:58:29 -05:00
Andreas Olofsson
a5b4768b3b Vectorizing edge2pulse module 2016-03-10 11:07:14 -05:00
Andreas Olofsson
e900ecca2a Simplifying clockdiv 
-tested in spi block
-more generic, simpler
 2016-03-10 11:06:28 -05:00
Andreas Olofsson
d129b93040 Adding edge specific pulse generators 2016-03-10 11:05:36 -05:00
Andreas Olofsson
8c350eed91 Debugged most of SPI 
-Changed to FIFO on TX path (cleaner)
-No good solution on RX with CDC since clock can stop, so you can't use an async fifo.
-Slave needs cleanup, rethink...
-Using commong par2ser and ser2par blocks
 2016-03-09 22:46:24 -05:00
Andreas Olofsson
ef790c1a59 Expanding par2ser functionality 
-module now works for multi bit shifts
-has been used in spi master module
-versatile load and shift bits
 2016-03-09 21:11:17 -05:00
Andreas Olofsson
e619bf9ef1 Making fifo safer 
-Blocking reads when fifo is empty
-Blocking writes when fifo is full
 2016-03-09 21:10:11 -05:00
Andreas Olofsson
e471850bd7 Adding table of content to README 2016-03-09 14:40:36 -05:00
Andreas Olofsson
d9f18e7b58 DV cleanup 
-removing all redundant build files, there must be only one...
 2016-03-08 21:23:02 -05:00
Andreas Olofsson
e549a63a04 Reorg/cleanup 2016-03-08 19:37:42 -05:00
Andreas Olofsson
6e22772420 Removed autoinst for dut.v 
-Had to remove the dummy dut.v to make scripts and links cleaner
 2016-03-08 19:36:44 -05:00
Andreas Olofsson
450f398065 Making xilinx default target for now 
-Need a cleaner way of dealing with define constants
 2016-03-08 19:35:44 -05:00
Andreas Olofsson
acce93fa0f Trying a better contention error message 
- Addding delayed sampling before displaying error
- Attempt to remove glitches
 2016-03-08 19:34:37 -05:00
Andreas Olofsson
e622aa1b33 Reorg 2016-03-08 15:49:54 -05:00
Andreas Olofsson
4dbf1a201e Adding configurable edge detector 2016-03-05 07:24:53 -05:00
RainerWasserfuhr
51976673c9 Update README.md 
typo
 2016-03-02 03:06:25 +01:00
Andreas Olofsson
274f5f93c6 Renamed C2C to MIO 2016-02-26 22:51:35 -05:00
Andreas Olofsson
a5194a30a3 Reorg 
-Renaming constants files as ".vh"
-Cleanup parameters
 2016-02-26 19:08:40 -05:00
Andreas Olofsson
67afb87881 Cleaning up sp memory changes 
-removing incorrect bist dout port
-repair vector name change
 2016-02-26 17:01:24 -05:00
Andreas Olofsson
d0171fd1d8 Adding ASIC interface to single port memory 
- Yes, I know this means more signals for others to "ignore". The fpga way to handle this is to auto generate hierarchy to hide the signals.
- I prefer a flatter structure with signals tied off and a library of known good components in a repo!
 2016-02-26 16:31:09 -05:00
Andreas Olofsson
5f9fea960a Changing interface for consistency 
-simple functions should strive for "in" and "out" parameters
 2016-02-25 15:02:53 -05:00
Andreas Olofsson
1c0646c569 Implemented absolute value function 2016-02-25 15:00:33 -05:00
Andreas Olofsson
39f8115df8 Adding bitreverse module 2016-02-25 14:50:43 -05:00
Andreas Olofsson
701b1deca3 Bug fix: adding missing event on reset 2016-02-25 14:43:00 -05:00
Andreas Olofsson
4900f2c6e2 Propagating clock during reset 2016-02-25 14:42:39 -05:00
Andreas Olofsson
2a22cd6ff8 Removing delay + clock gating 
- delay could hide bad designs..
- clock gating was hard to handle from outside
 2016-02-25 14:41:30 -05:00
Andreas Olofsson
8f37435d95 Instantiating parallel CRC calculators 2016-02-25 14:40:38 -05:00
Andreas Olofsson
1fa1e05754 Adding parallel CRC generators from @alexforencich 2016-02-25 14:40:02 -05:00
Andreas Olofsson
87848d5a14 Parity operator 2016-02-25 10:56:35 -05:00
Andreas Olofsson
ddfb4e00de Fixing generic fifo 
- This one is looking better
- Still needs more review. At least now it has a testbench...
 2016-02-24 14:26:25 -05:00
Andreas Olofsson
ea2ee15d5c Only run clock divider if enabled 2016-02-24 14:25:53 -05:00
Andreas Olofsson
d246529b4b Fixing sampling bug 2016-02-24 14:25:23 -05:00
Andreas Olofsson
cdef6141b4 Adding 2nd clock to interface 
- Randomizeing clock frequencies
- Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...)
- Don't be clever, be smart!
 2016-02-24 14:23:30 -05:00