Andreas Olofsson
117a4fee0d
Doing forall "dut*.v"
...
- Adding entries to a list gets old real fast....
2016-02-24 14:22:32 -05:00
Andreas Olofsson
fc7dc0e70a
Adding "SEED" as basic parameter
...
-making randomness clocks a first class citizen
-Verilog doesn't have a seed, need to drive it from the shell
-a must for async clocks, useful for many things
-does not preclude randomization externally as well
2016-02-24 14:21:04 -05:00
Andreas Olofsson
bb4a602f7f
New "dut files"
...
- new clocks (clk1 and 2)
- simpler names
- fifo dut
2016-02-24 14:19:57 -05:00
Andreas Olofsson
c9601a8f9c
Adding clk90 output to clkdiv
...
-Added testbench
-Needs more review!
2016-02-23 17:49:08 -05:00
Andreas Olofsson
84490be604
Adding testbench for clockdiv and gray converter
2016-02-23 17:17:41 -05:00
Andreas Olofsson
be22598935
Adding basic unit wiggle tests
2016-02-23 17:17:05 -05:00
Andreas Olofsson
852d7da490
Adding generic target
...
- all sims should have a "cfg file"
- since everything is configurable, this is the easiest way
2016-02-23 15:44:31 -05:00
Andreas Olofsson
5c66c16714
Reorg: moving generic fifo to separate file
...
- design was too "xilinx centric" before.
- library should work in any technology
2016-02-23 15:43:28 -05:00
Andreas Olofsson
91c662e528
Adding experimental fifo circuit
...
-not debugged
2016-02-23 15:42:55 -05:00
Andreas Olofsson
71efa8669f
Fixing new ddr circuits
2016-02-23 15:42:32 -05:00
Andreas Olofsson
98a14099ca
Fixing basic counter
2016-02-23 15:41:35 -05:00
Andreas Olofsson
8e466f3137
Adding debouncer circuit
2016-02-23 15:41:18 -05:00
Andreas Olofsson
e051d7d516
Adding vectorized iddr/oddr cells
2016-02-22 23:47:27 -05:00
Andreas Olofsson
fd7aff5dd8
Fixing warning messages in chip synthesis tool
...
- Don't fight the tools
- No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice.
- Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
2016-02-12 11:04:52 -05:00
Andreas Olofsson
b516a2cebf
Contributing nested interrupt controller
2016-02-11 22:04:36 -05:00
Andreas Olofsson
271e48d3c4
Fixing table formatting issue with logic
2016-02-07 18:09:47 -05:00
Andreas Olofsson
b5f0c775ff
Adding constants reference
2016-02-07 18:08:17 -05:00
Andreas Olofsson
e8678bb395
Adding commong docs directory
2016-02-03 23:14:32 -05:00
Andreas Olofsson
c8b9de9f42
Adding gpio and spi paths
2016-01-24 23:42:06 -05:00
Andreas Olofsson
083e459fb0
Fixing issue with empty ip list
2016-01-20 21:46:48 -05:00
Andreas Olofsson
abd25426b6
Fixing various small bugs
...
-sandbox accelerator working in simulation!
-t0+6 hrs wall time (lost 2 hours due to travel)
2016-01-20 17:23:09 -05:00
Andreas Olofsson
b3c0cdc082
Adding generic N:1 mux
2016-01-20 17:22:05 -05:00
Andreas Olofsson
1b6f1ecaef
Interface cleanups
2016-01-20 10:51:57 -05:00
Andreas Olofsson
21ac7b690d
Adding rd_counter to sync fifo interface
2016-01-20 10:50:00 -05:00
Andreas Olofsson
b26255dfb5
Fixing weird clog2 error in Vivado
...
-I guess you can't use built in function with localparam?
2016-01-19 14:07:04 -05:00
Andreas Olofsson
ca5db9fa4d
Interface cleanup
...
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
2016-01-19 13:33:08 -05:00
Andreas Olofsson
a270ade1cd
Cleaning up FIFO interfaces
...
-making sync/async interfaces more uniform
-removing valid signal, useless...
-preparing for count output
2016-01-19 13:28:47 -05:00
Andreas Olofsson
26a1304405
Fixing silly compiler errors
2016-01-17 21:15:28 -05:00
Andreas Olofsson
a1e19e0a5b
Adding time to debug message
...
- Very useful, should add these to all muxes!
2016-01-16 14:43:14 -05:00
Andreas Olofsson
8d6c07be9b
Changing timeout
...
- Test being cut off too early.
- Really need to implement end of test indication already!!!
2016-01-13 15:32:15 -05:00
Andreas Olofsson
bed1ba5556
Fixing write to TX register bug
...
- The write transaction was incorrectly piped through to axi slave
2016-01-11 20:50:40 -05:00
Andreas Olofsson
fa42bc6e2e
Reset simulation issue
...
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
2016-01-11 20:47:06 -05:00
Andreas Olofsson
307794711d
Error message in one hot mux
2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8
Changing dp memory interface in calling module
2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72
Making single/dual port memory interfaces constistant
2016-01-11 15:06:22 -05:00
Andreas Olofsson
4a454d71bd
Making AW main parameter
2016-01-11 15:05:21 -05:00
Andreas Olofsson
1d540e7b49
Adding comments to table
2016-01-10 17:06:08 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
c1da2531e6
Formatting
2016-01-10 15:18:40 -05:00
Andreas Olofsson
3168228174
Adding functionality for various modules
...
(Work in progress, not tested)
2016-01-10 13:33:31 -05:00
Andreas Olofsson
d5d315b5b9
Adding missing parameter
2016-01-10 11:59:14 -05:00
Andreas Olofsson
55eeafe0db
Compile cleanup
2016-01-10 11:58:54 -05:00
Andreas Olofsson
0568add03a
Changing emesh stimulus suffix ti "*.emf"
2016-01-10 11:57:38 -05:00
Andreas Olofsson
e9d3c78b17
Adding interfaces
2015-12-17 13:50:59 -05:00
Andreas Olofsson
2672519ab0
Adding memory to driver
...
-More modular, foudn myself adding memories in a lot of places
2015-12-17 12:53:20 -05:00
Andreas Olofsson
ec627556f7
Fixing basic FIFO bug
...
- count was not fully reset...
- adding parameter values to memory instance
2015-12-10 19:32:15 -05:00
Andreas Olofsson
22976b781d
Adding count/almost full to fifo
2015-12-08 21:10:17 -05:00
Andreas Olofsson
dd811ab417
Fixing unconnected wire bug
2015-12-05 09:01:18 -05:00
Andreas Olofsson
2d953d5639
Fixed unconnected wires in standby circuit
2015-12-04 17:32:15 -05:00
Andreas Olofsson
f5bb42dfe3
Moving axi cells to own folder
2015-12-04 03:38:26 -05:00
