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11 Commits

Author SHA1 Message Date
Andreas Olofsson
c0d8c967c4 Address remapping integration
Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
842a6d894a Fixing enable/reset:
-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
2015-04-23 18:01:19 -04:00
Andreas Olofsson
9e931c47ec Cleanup 2015-04-18 16:26:32 -04:00
Andreas Olofsson
18b2c489b0 Adding documentation to elink top level module 2015-04-17 22:10:14 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92 Fixed testbench bug (copy paste, RX not enabled)... 2015-04-17 10:08:17 -04:00
Andreas Olofsson
068d63279b Changing ESYSCLK definition (again.....)
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
2015-04-16 22:31:36 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
5bd5d1ff54 Man that's a lot of yak shaving....
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)

Now comes the fun part of testing
2015-04-13 23:35:21 -04:00
Andreas Olofsson
baebdab381 Reorganizing files...too many folders after all.
There is only one elink...
2015-04-11 00:10:16 -04:00