Andreas Olofsson
3102d6cd44
Adding comments
2015-11-16 09:58:47 -05:00
Andreas Olofsson
51c8ae600d
Burst works (really this time!!!)
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-Solved a speed path in synchronizing the wait signal, had to use the first edge signal fo the IO and the lclk_div4 for the core logic. It seems that the FPGA has a really hard time mixing clock domains, the routing delay between domains explodes
-Put in some special case logic for edge cases, like when there is a wait coming in from the IO and there is a wait from the IO. In that case, the packet gets sampled by the IO and not by the current logic.
-This needs to be cleaned up eventually, not clean enough but it's good enough for now.
2015-11-16 00:42:34 -05:00
Andreas Olofsson
5197822f53
Fixing burst logic speed path
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- The burst signal was going fro lclk_div4 domain straight into the io high speed domain. There is quite a bit of logic on this signal. Instead of starting with false paths or multi cycle paths with firstedge, I changed the pipeline.
2015-11-15 12:26:54 -05:00
Andreas Olofsson
f77938e9b0
Simplifying TX logic!!!!
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- The logic was a mess, causing me to go around in circles for days. In the end, by adding a missing sync circuit (duh!) between the fast and slow clock to align the edges and removing a redundant pipeline stage ("double") the nasty logic just fell away. Looks good now.
-Write bursts mostly works and design looks clean.
-one bug left to fix on streams of writes...
2015-11-15 01:35:46 -05:00
Andreas Olofsson
431abcda57
Removing write decode from wait pushback
2015-11-15 01:35:04 -05:00
Andreas Olofsson
df0deabd0f
Re-re-fixing the wait on RX
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- (fixing a temporary bad commit)
2015-11-15 01:34:20 -05:00
Andreas Olofsson
c1beed9a13
Two more wait bugs for burst
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- The burst signal needs to be pipelined like everything else (0th order..)
- Don't look at write signal when pushing back wait...WILL GO BACK AND REVISIT THIS ONE LATER.
- Yeah, burst write test now passes!!!!
2015-11-13 17:26:05 -05:00
Andreas Olofsson
52b328c194
Redesign of elink transmitter
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- Old design was not workable with bursting and long waits. The wait signal needs to be very carfully handled since it's asynchronous to the clock.
-The TX needs to be stopped quickly so the sync needs to be done at the high speed clock, not at div4 clock
-Since there are synchronizers here, there should be only one point of sync. This is not completely the case still, but I think??? it should be safe by constructiona at this point.
-bursting working at this point for writes!!!!!
2015-11-13 16:31:59 -05:00
Andreas Olofsson
78a72aa428
fixing packet format for remap block
2015-11-13 16:31:29 -05:00
Andreas Olofsson
a335194dea
fixing packet reshuffling bug
2015-11-13 16:30:33 -05:00
Andreas Olofsson
f7806821c7
Various wait cleanups in RX
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- using rx reset, safer as this stays in reset longer, until the clock has hade time to clean up the rest
2015-11-13 16:28:40 -05:00
Andreas Olofsson
4637f90546
Fixing wait circuit in dut (randome wait gen was removed from top)
2015-11-13 16:27:06 -05:00
Andreas Olofsson
fbcf58d642
Adding description for wait signal
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- Also fixing packet description
2015-11-13 16:26:32 -05:00
Andreas Olofsson
9dbaeaedcd
adding hello world test for elink, always run this first
2015-11-13 16:24:59 -05:00
Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
8820c8500a
Adding wait circuit for axi/elink
2015-11-12 10:47:52 -05:00
Andreas Olofsson
3b2968f162
Clean up test files
2015-11-12 10:46:52 -05:00
Andreas Olofsson
60bdda4dfa
Dead simple test
2015-11-12 00:59:21 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
07dff85090
Changing build script to work with xilinx model
2015-11-12 00:56:02 -05:00
Andreas Olofsson
1dcd9a82bd
Fixing burst transmit bug
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- The burst should be interrupted as soon as there is a wait signal. When the wait stops, a new frame naturally starts.
2015-11-11 22:33:54 -05:00
Andreas Olofsson
4a7b0d8f1c
Adding proper test or bursting
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- Need to at a minimum try to fill the fios
- Need to add a wait circuit at the back end of fifo to test pipe
2015-11-11 22:28:53 -05:00
Andreas Olofsson
dccaadc286
Updating register names and fixing error in description of RXCFG
2015-11-11 14:26:46 -05:00
Andreas Olofsson
1ddbc4c0a8
Adding missing register
2015-11-11 14:26:35 -05:00
Andreas Olofsson
867b750c50
Adding write from stimulus to dv link1
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- also, more cleanup of ID parameters
2015-11-11 14:02:02 -05:00
Andreas Olofsson
c885745f6c
Fixing half/byte zero-out bug
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- Interrupted mid coding apparently..
- Upper bits need to be zeroed out for 8/16 bit read responses
2015-11-11 14:00:13 -05:00
Andreas Olofsson
4885c3f7d2
Adding byte/halfword test
2015-11-11 13:58:55 -05:00
Andreas Olofsson
0a2ea66b7e
Bug fix. Adding missing ID parameter.
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- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
9c1fb038a9
Adding test for remapping logic
2015-11-11 13:57:18 -05:00
Andreas Olofsson
9feaa36dce
Refactoring and adding some tests
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- "infinite loop test"
- separating out common elink functions
-
2015-11-11 05:32:06 +00:00
Andreas Olofsson
e3544c4fc8
Adding toggle led test
2015-11-11 03:41:22 +00:00
Andreas Olofsson
b1e3a39d06
adding legacy mode registers
2015-11-11 03:39:17 +00:00
Andreas Olofsson
e097da6bda
Removing reset sequence from access utility
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- Responsibility of application
- Makes no sense resettting device after each write/read..
2015-11-11 03:36:55 +00:00
Andreas Olofsson
b2926fdc5e
Adding test for setting east link to half speed
2015-11-10 22:30:41 -05:00
Andreas Olofsson
d2d291a0fc
Merge branch 'master' of https://github.com/parallella/oh
2015-11-10 22:30:10 -05:00
Andreas Olofsson
7f0698bbc8
Fixed ctrlmode bug
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- Found this by trying to toggle the LED in hardware!!
- So freaking close!!
2015-11-10 22:29:30 -05:00
Andreas Olofsson
6b2f6f42bc
Added missing init() routine
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- Version 0 is the one currently in production, works!!!
- Now starting to debug the new linke (verion 1)
2015-11-11 02:00:14 +00:00
Andreas Olofsson
f92bcb3f0b
Adding elink register include file
2015-11-10 18:48:53 -05:00
Andreas Olofsson
8c4a02fbdf
Adding bringup script for elink
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- uses 104 bit packet for formatting
- makes for easy transition from verilog testbench
- happy with this one...
2015-11-10 17:01:04 -05:00
Andreas Olofsson
5840c3e369
Fixing reset bug
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- There is a register reset by out_clk reset on fifo_cdc
- This means the config path needs to us rx synched reset to be clean
2015-11-10 09:19:45 -05:00
Andreas Olofsson
f2b2c4fd00
Balancing TXclocks
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- Better to be balanced with clocks (BUFG) than trying with BUFIO and having CDCs. Tools warned about it...
2015-11-10 09:19:01 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
243ba6b608
Speedpath fix for rx io
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- reduce fanout on IDDR block
2015-11-09 21:56:46 -05:00
Andreas Olofsson
efef6448c2
Fixing wait bug on config write (2 bugs)
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- missing reset on wait signal
- missing wait on cfg
2015-11-09 21:55:46 -05:00
Andreas Olofsson
ef204a875b
Fixed register read/write test
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- Has been tested with dv_axi to work
2015-11-09 20:39:57 -05:00
Andreas Olofsson
02ae7cf83d
Cleanup
2015-11-09 20:39:48 -05:00
Andreas Olofsson
6dcd5e96bf
Cleanup after lock width change for zynq axi
2015-11-09 20:39:16 -05:00
Andreas Olofsson
e2c917b6f9
Fixed packet reformatting bug
2015-11-09 20:38:55 -05:00
Andreas Olofsson
497dd71aaa
Fixed readback bug
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- there were hard coded magic number in code, bad practice!
- now works!
2015-11-09 20:38:12 -05:00
Andreas Olofsson
13d29f8e67
Stupid typos..
2015-11-09 16:18:20 -05:00
