Andreas Olofsson
665876cfb4
Adding bursting to test bench
2015-05-18 15:37:46 -04:00
Andreas Olofsson
36696e709e
Updates for new interface
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-shortening to fit new clock
2015-05-12 07:42:56 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
6b2d479692
DV environment cleanup
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-removed floating signals
-blocking ID transactions from reaching memory (should be done in real design as well)
2015-04-28 16:55:12 -04:00
Andreas Olofsson
3567805823
Adding dummy vector to testbench
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-All zeroes is ignored by stimulus
-Easy to remember...
2015-04-27 11:13:53 -04:00
Andreas Olofsson
c0d8c967c4
Address remapping integration
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Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
ec68dddd99
Packet interface changes
2015-04-23 18:09:16 -04:00
Andreas Olofsson
fc3926ceb1
Added wait signal for reads
2015-04-21 17:13:53 -04:00
Andreas Olofsson
643ceed432
Adding manual test feature to testbench
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-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
2015-04-18 16:14:53 -04:00
Andreas Olofsson
08a31cd971
MILESTONE: Open souce simulation elink loopback working!
2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92
Fixed testbench bug (copy paste, RX not enabled)...
2015-04-17 10:08:17 -04:00
Andreas Olofsson
dca611c5ba
Getting all the clk config numbers aligned
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Not changing these again!!
2015-04-16 22:48:31 -04:00
Andreas Olofsson
068d63279b
Changing ESYSCLK definition (again.....)
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old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
2015-04-16 22:31:36 -04:00
Andreas Olofsson
b1a9f502ca
Xilinx models
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-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench
2015-04-15 17:54:19 -04:00
Andreas Olofsson
846bfa3357
Fixing startup issues in transmit path:
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-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
2015-04-15 16:33:20 -04:00
Andreas Olofsson
b58660e9a6
Adding different data modes
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Good enough fufu testing...
..the next step is driving stimulus with transactor through Verilator..
2015-04-14 23:47:49 -04:00
Andreas Olofsson
b9d3c5ac5c
Verilator lint cleanup
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~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
bf1671b1e9
Added "fufu" DV environment for elink
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-Icarus for now, verilator comes next
-Using our "standard" emesh interface
..here we go...
2015-04-14 11:45:33 -04:00
