- holding rx in reset state until tx is done
- removing reset from all pipeline registers
- removing reset from oddr/iddr
- the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link. Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing the link interfac?
* Add an ifdef to bypass the fifos?
-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
-A read on transmit side initiates timer
-Timer is reset when read request comes back
(assumption last read requests starts timer..last return stops it)
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)
Now comes the fun part of testing
Our "standard packet" order should be followed everywhere to ease verification and integration (standards are good fir reuse...):
[0]=access
[1]=write
[3:2]=datamode
[7:4]=ctrlmode
[39:8]=dstaddr
[71:40]=data
[103:72]=upper-data (or srcaddr)
