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14 Commits

Author SHA1 Message Date
Andreas Olofsson
3683c39e5b Bug fix. Fifo read delay not accounted for
-Added valid signal to fifo
2015-04-27 11:16:15 -04:00
Andreas Olofsson
f7aef66f29 Bug fix: erx pipeline misalignment
-access signal happens one signal after empty goes low to compensate for fifo data latency
-verify that this is how the Xilinx FIFO works as well.
2015-04-26 08:31:36 -04:00
Andreas Olofsson
c0d8c967c4 Address remapping integration
Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
3b637e55f0 MILESTONE: Design once again passes test
New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
5c8fb41849 Fifo read bug
-fifo should be read when it's not empty and there is no wait pushback
2015-04-23 20:07:10 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
ed0b8c2539 Major RX change:
-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
Andreas Olofsson
9e931c47ec Cleanup 2015-04-18 16:26:32 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92 Fixed testbench bug (copy paste, RX not enabled)... 2015-04-17 10:08:17 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
5bd5d1ff54 Man that's a lot of yak shaving....
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)

Now comes the fun part of testing
2015-04-13 23:35:21 -04:00
Andreas Olofsson
d45439b43e Changing emesh/elink transaction order
Our "standard packet" order should be followed everywhere to ease verification and integration (standards are good fir reuse...):
[0]=access
[1]=write
[3:2]=datamode
[7:4]=ctrlmode
[39:8]=dstaddr
[71:40]=data
[103:72]=upper-data (or srcaddr)
2015-04-12 08:59:53 -04:00
Andreas Olofsson
baebdab381 Reorganizing files...too many folders after all.
There is only one elink...
2015-04-11 00:10:16 -04:00