Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
Andreas Olofsson
a3cfa17b06
Removing old module
2015-05-04 22:38:28 -04:00
Andreas Olofsson
de74f8accc
Removed synchronizer, not needed
2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f
Baking in the IO wait signal into rd/wr wait
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-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
Andreas Olofsson
0aba754b7e
Cleanup
2015-05-04 10:54:42 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
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Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833
Blocking TX outgoing transcations on LINKID match
2015-05-04 10:41:14 -04:00
Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
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Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
781121fc61
Cleanup
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-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a
Fixed verilog syntax issue
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-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111
Clock/reset fixes
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-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd
Fixing ecfg_clocks
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-Was missing clock connection
-Adding ID to match only to the right transcations
2015-05-02 22:40:27 -04:00
Andreas Olofsson
ebd9a89afd
Adding constants to handle model
2015-05-02 21:30:26 -04:00
Andreas Olofsson
e5fc895a25
Cleanup
2015-05-01 18:33:29 -04:00
Andreas Olofsson
340d99cab1
Instance renaming
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Will help with FPGA synthesis reports (uniqueness needed sometimes)
2015-05-01 18:19:36 -04:00
Andreas Olofsson
8461277ab1
Complete redesign of configuration register file
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-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
Andreas Olofsson
f215e07ce9
Updated to fit new ERX_RR register
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-Read response now returns to a memory mapped register
2015-05-01 17:53:55 -04:00
Andreas Olofsson
23cb2acb31
Updated constants file to fit new register map
2015-05-01 17:52:55 -04:00
Andreas Olofsson
4059a6eaa2
Created unified one clock modular confi for RX/TX
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-Solves clock domain crossing uglyness
-Very nice and clean!!
-Only compromise is that the RESET and CLOCK registers aren't readable
2015-05-01 17:51:12 -04:00
Andreas Olofsson
20534a6ed1
Added testmode to transmitter
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-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
2015-05-01 17:47:24 -04:00
Andreas Olofsson
0ca303432b
Cleanup
2015-05-01 17:31:45 -04:00
Andreas Olofsson
e168bd5f98
reorg
2015-05-01 17:21:45 -04:00
Andreas Olofsson
0762b90fef
Reorg
2015-05-01 17:21:21 -04:00
Andreas Olofsson
5f15ed220d
Changing name
2015-05-01 14:42:15 -04:00
Andreas Olofsson
ad401d09e0
??
2015-04-30 23:35:01 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
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Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
3ef05ad63a
Register map twiddling..
2015-04-28 17:00:17 -04:00
Andreas Olofsson
d00d58d116
Read response now a readable memory mapped register
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Much better...hidden addresses SUCK!
2015-04-28 16:58:45 -04:00
Andreas Olofsson
2460aa9247
Bypass erx remap on all ID matches
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Not just for read responses..
2015-04-28 16:58:05 -04:00
Andreas Olofsson
a6ac9b4666
Added bit to etx_remap
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-To enable writing to ERX, we need to include the group number
-support groups F,E,D,C (bits [19:18])
2015-04-28 16:56:31 -04:00
Andreas Olofsson
a2ceb8ff6e
Cleanup, two-link environment working
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-Write to config registers from RX path now working
2015-04-28 00:47:26 -04:00
Andreas Olofsson
02812c03a8
Fixing bug on 64 bit register write
2015-04-28 00:46:40 -04:00
Andreas Olofsson
0431d79992
Enabling RX always
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-Should we ever turn this off?
2015-04-28 00:45:16 -04:00
Andreas Olofsson
96c35c4908
Removing filter for rxwr_access
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-Needed to enable simple mi_write interface on RX
2015-04-28 00:44:20 -04:00
Andreas Olofsson
f544c44a08
Adding register access from RX
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-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
2015-04-27 23:51:00 -04:00
Andreas Olofsson
6b108f5e1f
Adding reset to synchronizer
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(cause there may not be a clock...)
2015-04-27 16:03:57 -04:00
Andreas Olofsson
df53a2dc4f
Adding missing reset
2015-04-27 16:03:12 -04:00
Andreas Olofsson
a1722b7ae6
Adding timeout circuit
2015-04-27 16:02:15 -04:00
Andreas Olofsson
c9124f415b
Added "timeout" to elink interface
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-Use as error interrupt?
-Is there another method for checking error?
2015-04-27 15:11:56 -04:00
Andreas Olofsson
b0116c9316
Added read watchdog timer
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-A read on transmit side initiates timer
-Timer is reset when read request comes back
(assumption last read requests starts timer..last return stops it)
2015-04-27 13:00:00 -04:00
