Use IRQ_F2P for interrupts, this is what other designs seem to do.
Use interrupt pin 11 (maps to IRQ=87 devicetree-IRQ=55 (87-32)).
Disable CORE0_FIQ_INTR as we no longer use it.
Add concat ip, apparently needed:
http://www.xilinx.com/support/answers/58942.html
Add constant_zero, and constant_one outputs to parallella_base module.
Tie all unused (by PL) interrupts on the F2P port to 0.
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Add test for writes to same address. Apparently consecutive 64-bit
writes to the same address can turn into burst writes.
From:
https://github.com/parallella/oh/issues/37
Andreas:
> Remembered that we have a long forgotten mode in the epiphany chip elink
> (not impemented in the fpga elink) that creates bursts when you write
> doubles to the same address. (F**K!)
> So the writes were likely coming in as bursts.
> Looks like the mailbox works fine when you write in "int"s (I tested it on
> the board with consecutive)
> (see "mailbox_test" in elink/sw0)
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
-The current testbench has a big pause between frames, whereas the chip might push out back to back frames with only a single cycle pause between frames. It seems possible that the old logic would have been a problem, since there two incorrect states that took 2 cycles to settle. This would not have been a problem with bursting or frames with many nops between. Let's see....
-The correct way to verify this is to 1.) Improve TX to make performance as good as on the chip (less stalls) 2.) Create a testbench witht the chip reference code.
-In the meantime, we compile and pray...
-This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this.
-Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
