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Author SHA1 Message Date
Andreas Olofsson
10cad20205 Merge pull request #78 from olajep/spi-fpga-project 
SPI fpga project
 2016-05-04 14:24:55 -04:00
Ola Jeppsson
6c7e09fc66 spi: Add FPGA project 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-04 20:13:15 +02:00
Ola Jeppsson
cc50698004 spi: Add parallella_spi top module 
Note:
spi_s_sclk must map to a SRCC/MRCC capable pin.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-04 20:13:15 +02:00
Ola Jeppsson
47d384db4c spi: Add axi_spi module 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-04 19:05:16 +02:00
Andreas Olofsson
99cc9279c4 Merge pull request #77 from olajep/linux-gpio-driver 
GPIO: Update Linux driver
 2016-05-03 18:44:24 -04:00
Andreas Olofsson
9bae970ae9 Merge pull request #76 from olajep/gpio-fpga-project 
GPIO: Fix incorrect documentation for ITYPE register
 2016-05-03 18:43:01 -04:00
Ola Jeppsson
909f7feabf GPIO: Update Linux driver 
Branch with full history here:
https://github.com/parallella/parallella-linux/tree/oh-gpio

ChangeLog:

commit eb190fa4891cf2c2d33f263d51c566ebb15ac9a1
Author: Ola Jeppsson <ola@adapteva.com>
Date:   Tue May 3 23:27:52 2016 +0200

gpio: oh: Interrupt detection is disabled for masked interrupts

The OH GPIO controller disables interrupt detection for masked
interrupts so we don't need to provide a irq_enable() to protect from
spurious interrupts.

Nor do we need to mask ILAT against IMASK to get pending interrupts in
the interrupt handler.

commit 366257c1893199d3dba5f3768df8b235d702f56e
Author: Ola Jeppsson <ola@adapteva.com>
Date:   Tue May 3 23:18:50 2016 +0200

gpio: oh: Fix mix-up of level/edge interrupt types

The OH GPIO documentation incorrectly states that level type interrupts
are the default, when it's the opposite (edge) in RTL code.

commit ecd55cda6ea9967fb98cf89f1f6c622d2ac8d390
Author: Ola Jeppsson <ola@adapteva.com>
Date:   Tue May 3 19:35:10 2016 +0200

gpio: oh: Remove irq member from struct oh_gpio

We only use the irq number in oh_gpio_probe(), after that it's managed
by devm.

commit 582ab5097fe59b389218deb509619bfc313cab27
Author: Ola Jeppsson <ola@adapteva.com>
Date:   Fri Apr 29 15:17:49 2016 +0200

gpio: oh: Limit to 32-bit register access if possible

Limit to 32-bit register access when ngpios is less than 32.  Current
oh-gpio HDL code does not support split access to the upper 32-bits of a
register, so right now we're limited to 32 GPIOs on 32-bit
architectures.

commit 5cb10394ba6b524c6acfe82e7481d86473ace453
Author: Ola Jeppsson <ola@adapteva.com>
Date:   Fri Apr 29 13:45:46 2016 +0200

gpio: oh: Add ngpios property

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-04 00:19:15 +02:00
Ola Jeppsson
0ca46caf4f GPIO: Fix incorrect documentation for ITYPE register 
Edge is default.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-03 20:44:07 +02:00
Andreas Olofsson
82255b1318 Merge pull request #75 from olajep/gpio-fpga-project 
Gpio fpga project
 2016-05-03 13:35:53 -04:00
Ola Jeppsson
598fa0dc7d GPIO: Connect IRQ in FPGA design 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-03 17:06:04 +02:00
Ola Jeppsson
e30678f2d3 GPIO: Add zero and one constants to parallella_gpio 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-03 17:06:04 +02:00
Ola Jeppsson
806be9db5c GPIO: Fix pin constraints for FPGA project 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-03 15:38:51 +02:00
Ola Jeppsson
1c0c72d964 GPIO: parallella_gpio: Fix pin direction 
Connect gpio directly to pgpio.
The oh_tristate block was never needed.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-05-03 14:42:22 +02:00
Andreas Olofsson
84dc26bb14 Merge pull request #74 from olajep/gpio-fpga-project 
Gpio fpga project
 2016-04-29 12:42:05 -04:00
Ola Jeppsson
feffddb166 GPIO: Update FPGA project to use parallella_gpio as top 
Use parallella_base pin constraints.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-29 18:03:41 +02:00
Ola Jeppsson
13f0f7984b GPIO: Add parallella_gpio module 
Parallella board top module.
Uses pgpio from parallella base.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-29 18:02:31 +02:00
Ola Jeppsson
b6cd729b20 common: Add oh_tristate module 
Function: Bidirectional port with output-enable

Not tested.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-29 18:01:20 +02:00
Ola Jeppsson
80f7befb2a GPIO: Fix access/wait/packet signals in AXI module 
Need mux for rd_access and wr_access.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-29 17:56:57 +02:00
Ola Jeppsson
0c91885643 GPIO: Add FPGA project 
Add FPGA project for Vivado.
It compiles but not tested.

TODO:
gpio_in / gpio_out are not connected.
Interrupt not connected.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-28 00:49:50 +02:00
Ola Jeppsson
78422215e7 GPIO: Add AXI GPIO module 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-28 00:48:41 +02:00
Ola Jeppsson
de8d7b7132 GPIO: Fix hardcoded address width 
Use parameter value (which can be smaller).

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-28 00:35:38 +02:00
Andreas Olofsson
22f36ce93d Merge pull request #69 from olajep/linux-gpio-driver 
Linux gpio driver
 2016-04-22 08:24:31 -04:00
Ola Jeppsson
2ae9c2420a GPIO: Add linux kernel driver 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-22 13:39:50 +02:00
Ola Jeppsson
0ecf9087a0 GPIO: Move gpio library to separate directory 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-22 13:02:00 +02:00
Andreas Olofsson
23cdb8d8d4 Adding clock mux with integrated clock gater 2016-04-19 22:55:29 -04:00
Andreas Olofsson
5e8c53f619 Tweaking isolate block 
- removing power signals for now
- adding asic parameter
 2016-04-19 22:54:30 -04:00
Andreas Olofsson
8e23abbc98 Standby bug fix (floating clk) 2016-04-19 22:54:00 -04:00
Andreas Olofsson
05f73e200d Improving standby circuit 
- removing reset (bad logic)
- refactor for simplicity/clarity
- interface changes
 2016-04-19 16:23:50 -04:00
Andreas Olofsson
2d3fb8d94c Making clock gater asic friendly 
- removing reset, shouldn't be in logic
- instantiating asic integrated clock gating cell
- removing vectorization, shouldn't be here
 2016-04-19 16:19:26 -04:00
Andreas Olofsson
6742976401 Fixing more synthesis warnings 2016-04-17 10:37:08 -04:00
Andreas Olofsson
4e513cfcce Fixing synthesis compilation warnings 
- Could supress warning printout, but you can't control people's synthesis scripts. Better to fix once than N times...
 2016-04-17 09:49:07 -04:00
Andreas Olofsson
96e13629aa Fixing standby block 
- Was missed because block was never instantiated...
- Iverilog not very particular..not a great linter
 2016-04-17 09:47:55 -04:00
Andreas Olofsson
8b24139be1 Adding ASIC parameter to special library functions 
- Needed to map to specific proprietary libraries
- Need to hide actual cells behind abstraction due to NDA
 2016-04-15 23:25:49 -04:00
Andreas Olofsson
3314051934 Adding delay cell 2016-04-15 23:25:16 -04:00
Andreas Olofsson
a330f73838 Fixing readme 2016-04-15 22:38:06 -04:00
Andreas Olofsson
397b10946f Shortening flow names 
- + reorg
 2016-04-15 22:32:27 -04:00
Andreas Olofsson
09e40875bb Adding wrappers for pnr 2016-04-15 18:01:09 -04:00
Andreas Olofsson
8bfccdfd73 Simplifying synthesis flow 
- Too many steps, some of them were "one line long"
 2016-04-15 17:37:32 -04:00
Andreas Olofsson
53dea826bc Merge branch 'master' of github.com:parallella/oh 2016-04-14 15:55:16 -04:00
Andreas Olofsson
d237c17eba Instantiating generic ram module in dp memory 2016-04-14 15:54:50 -04:00
Andreas Olofsson
f9910d6094 Fixing depth parameter in fifo 2016-04-14 15:54:23 -04:00
Andreas Olofsson
b70b9de811 Merge pull request #65 from olajep/vivado-localparam-clog2-fix 
Vivado doesn't like localparam / clog2 combo
 2016-04-14 15:53:35 -04:00
Andreas Olofsson
305c63c911 Merge pull request #64 from olajep/merge-stable 
Merge stable into master
 2016-04-14 15:53:19 -04:00
Ola Jeppsson
62469afc4b Vivado doesn't like localparam / clog2 combo 
Using parameter instead works.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 21:46:14 +02:00
Ola Jeppsson
652f928377 Merge branch 'stable-prepared' into merge-stable 
Conflicts:
      parallella/fpga/headless/Makefile
      parallella/fpga/headless/bit2bin.bif
      parallella/fpga/headless/build.sh
      parallella/fpga/headless/dummy.elf
      parallella/fpga/headless/parallella.bit.bin
      parallella/fpga/headless/run.tcl
      parallella/fpga/sdr_fmcomms/run.tcl
      src/accelerator/fpga/bit2bin.bif
      src/accelerator/fpga/dummy.elf
      src/parallella/dv/build.sh
      src/parallella/fpga/Makefile
      src/parallella/fpga/headless_e16_z7010/Makefile
      src/parallella/fpga/headless_e16_z7010/bit2bin.bif
      src/parallella/fpga/headless_e16_z7010/build.sh
      src/parallella/fpga/headless_e16_z7010/dummy.elf
      src/parallella/fpga/headless_e16_z7010/run.tcl
      src/parallella/fpga/headless_e16_z7020/Makefile
      src/parallella/fpga/headless_e16_z7020/build.sh
      src/parallella/fpga/headless_e16_z7020/parallella.bit.bin
      src/parallella/fpga/headless_e16_z7020/parallella_e16_headless_gpiose_7020.bit.bin
      src/parallella/fpga/headless_e16_z7020/run.tcl
      src/parallella/fpga/sdr_fmcomms/run.tcl

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:41:47 +02:00
Ola Jeppsson
4c9f3273b1 Move parallella to src/ 
Move parallella to src/ to prepare for merge with master.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:30:46 +02:00
Ola Jeppsson
8171b9023a src/parallella/fpga: Rename headless to headless_e16_z7020 
Set up paths for merge with stable

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 20:26:34 +02:00
Andreas Olofsson
6b72eab0fe Merge pull request #63 from olajep/e16-z7010-headless 
E16 z7010 headless
 2016-04-14 13:52:42 -04:00
Andreas Olofsson
e66c526fec Merge pull request #62 from olajep/gpio-driver 
GPIO: Remove direction cache variable
 2016-04-14 13:00:48 -04:00
Ola Jeppsson
dccfe3d0b4 GPIO: Remove direction cache variable 
Not needed now that GPIO_DIR is readable.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-04-14 18:57:31 +02:00